PAL16L8
JLB/CJTC 14AUG86
44302B,11D,LBC1

/Q0 /Q2 /CC2 /BDRY25 /BDRY50 /CGNT /CGNT50 /CACT /TERM GND
/BGNT /CGNTCACT /RT /IORQ TEST NC16 /DSTB /EMD /BGNTCACT VCC

IF (/TEST) EMD = Q2 * Q0 * CACT         ; CPU CYCLE TO BUS SET
            + EMD * CACT                ;       "          HOLD
            + CGNT * CGNT50             ; CPU CYCLE TO MEM SET
            + EMD * RT * CC2 * /TERM    ; ) HOLD TERMS FOR
            + EMD * IORQ * CC2 * /TERM  ; ) CPU READ, FETCH AND
                                        ; ) MAP CYCLES

IF (/TEST) CGNTCACT = CGNT + CACT

IF (/TEST) BGNTCACT = BGNT + CACT

IF (/TEST) DSTB = CGNT + CACT * /BDRY50 * /BDRY25 * /IORQ
                      + CACT * IORQ * CC2          ; IOX CYCLE



DESCRIPTION

; 060387 JLB: EMD WAS HOLDING IN ADDRESS PART OF IOX CYCLES AFTER
; BUFFERED WRITE CYCLES.
; EMD - ENABLE DATA PATH BETWEEN CD AND LBD
; 270387 CJTC: NEW SIGNAL DSTB TO SAMPLE DATA AT LBD/CD BUFFERS ON
; CPU FROM BUS READ, AT BDRY.
; 040487 JLB: DSTB MUST NOT CLOCK DATA BEFORE CACT GOES OFF IN IOXES.
;  (NEGATIVE SETUP OF DATA IN BUS SPECS.)
;
; 180587 CJTC: 3202B
; 070887 JLB: 3202C ONLY! (TEST MODE).