PAL16L8
JLB 26NOV86
44305D,15F,CSCTL

/FORM /CC1 /CC2 /CC3 /LCS /RWCS /WCS FETCH /BRK GND
/TERM /WCSTB LUA12 /WCA /ELOW /EUPP /EWCA /ECSL /WICA VCC

; CONTROL STORE CONTROL

IF (VCC) WICA = WCA * FETCH * /TERM                 ; WRITE PULSE TO MICROINTRUCTION CACHE

IF (VCC) WCSTB = /CC3 * CC2 * CC1 * WCS * RWCS      ; e+f WRITE PULSE TO WRITEABLE
               + CC3 * /CC2 * CC1 * LCS             ; m+n WRITE PULSE DURING LOAD CONTROL

IF (VCC) ECSL =  RWCS * /WCS * CC3 * /TERM          ; READ CONTROL STORE HOLD
              + RWCS * /WCS * /CC1 * CC2 * /TERM    ; HOLD OVERLAP WITH EWCA

IF (VCC) EWCA = RWCS * /CC3 * CC2 * /TERM           ; ENABLE WCA REG. IN MIC ONTO MA
              + RWCS * /CC3 * CC1 * /TERM           ; AVOID BLIP ON NEXT CYCLE

IF (VCC) EUPP = LUA12                               ; NORMAL ADRESSING
              + WCA * FETCH                         ; WRITE INTO MICROINSTUCTION CACHE
              + FETCH * /CC1 * /CC2 * /CC3 * /TERM  ; ENABLE IN THE FIRST 50NS
                                                    ; + HOLD TIME = 75NS

                                                
IF (VCC) ELOW = /LUA12 * /FETCH                     ; NORMAL ADRESSING. ON FETCH EITHER MI
              + /LUA12 * TERM                       ; ENABLE ACCORDING TO LUA12 BEFORE FET
              + FORM * /BRK * CC2 * /TERM           ; OR A MAP IS USED.
              + FORM * /BRK * CC3 * /TERM           ; DO A MAP
              + /LUA12 * BRK * CC2 * /TERM          ; ON BRK: USE BANK SELECTED BY LUA12.
              + /LUA12 * BRK * CC3 * /TERM          ;

DESCRIPTION

; 130387 JLB: ELOW ALWAYS ENABLED ON TERM IF LUA12 IS LOW.
; MAY SPEED UP NON FETCH CYCLES.

; 180587 3202B
; 090687 JLB: EWCA MUST NOT BE ENABLED DURING a AND b. WILL CREATE BLIP ON
; NEXT CYCLE.
; 090687 JLB: ECSL HOLD IN g AND h.
; 030987 JLB: WRITE IN CONTROL STORE DOES NOT WORK. WRITE PULSE STARTS TOO
; SOON. WCSTB CHANGED TO e+f IN THIS CASE, AND TO m+n DURING LCS
; TO BE ABLE TO USE 250ns PROMS.