PAL16L8
ADGD 13/8/86
44310D,3F,LBDIF

/HIEN /BGNT /CGNT /LOEN /CGNT50 ECCR /BGNT50 /BGNT75 /BDAP50 GND
/MR RDATA /MWRITE50 /BIOXE /REF100 RAS /BIOXL /BDRY /BCGNT50R VCC

IF (VCC) BCGNT50R = /MWRITE50 * BGNT * BGNT50    ; FROM 50NS AFTER GNT ON READ C
                  + /MWRITE50 * CGNT * CGNT50    ; LASTS FOR THE REST OF THE CYC

IF (VCC) BDRY = /MWRITE50 * BDAP50 * BGNT * /LOEN * /HIEN * /RAS  ; BUS READ FROM LOCAL MEM
              + MWRITE50 * BDAP50 * BGNT50 * BGNT                ; BUS WRITE TO LOCAL MEM
              + BIOXL * ECCR                                     ; IOX=ECCR
              + /MR * BDRY * BDAP50                              ; HOLD TERM FOR MEMORY
              + /MR * BDRY * BIOXE                               ; HOLD TERM FOR IOX CYCLE
              + REF100
              + /MWRITE50 * BDAP50 * /BGNT50 * BGNT75            ; LATE BDRY FOR 10MHZ DISK

IF (VCC) BIOXL = BIOXE * /BGNT * /CGNT

IF (VCC) /RDATA = MWRITE50 ; INDICATES DATA READY ON
    	        + LOEN
                + HIEN
                + /BGNT * /CGNT
                + RAS

DESCRIPTION

;280287 JLB: ECCR WRONG POLARITY, RESPONDS WITH BDRY TO
;EXISTING IOX-ES.
;280287 JLB: NEW INPUT REF~ , TO GENERATE A REF PULSE OF 175-200NS
;DURATION BY GENERATING BDRY.
;
;180587 M3202B
;090787 B JLB: RAS USED IN RDATA TO AVOID SPIKE ON TRANSITION FROM
;              LOEN TO HIEN.
;290787 C JLB: BD HAD A TYPICAL SETUP TIME OF 140NS BEFORE BDRY ON DMA READ
;              CHANGED TO 65NS (25NS REQUIRED). DMA BUFFERED WRITE: BDRY START
;              50NS AFTER BGNT GOES ACTIVE ON DMA WRITE, AND LASTS UNTIL BGNT
;              OR BDAP50 GOES OFF (105NS MIN.}. THIS IS TO GIVE TIME FROM
;              GRANT OFF TO BMEM ON IN THE FOLLOWING CYCLE.
;110887 D JLB: BDRY GAN BE LOST IF BDRY50 IS NOT PRESENT AT THE TIME STATE
;              7 IN THE RAM CONTROL IS REACHED. HAPPENS WITH 1OMHZ DISK CONTR.
;              SINTRAN STOPS ON LEVEL 14 DURING STARTUP.