PAL16R4
JLB 26NOV86
44403C,15D,CYIN0

CLK CSDELAY0 CSDLY CSECOND CSLOOP /ACOND /MR LUA12 /MAP GND
/OE /NC12 /SLCOND /DMAP /DMA12 /MDLY /LCS /NC18 /DLYO VCC

; CYCLE CONTROL INPUT GENERATOR. PART 0.

IF (VCC) DLY0 = MDLY                 ; 25NS DELAY ON MICROCODE REQUEST
              + CSDELAY0             ; 25NS DELAY ON PREVIOUS CYCLE ON MICROCODE REQ
              + ACOND * CSECOND      ; CONDITIONAL MICROSEQUENCING
              + ACOND * CSLOOP       ; USING ALU RESULT
              + LUA12 * /DMA12       ;
              + /LUA12 * DMA12       ; CHANGING FROM LOWER TO UPPER CONTROL STORE A     
              + DMAP                 ; AFTER MAP TO AVOID CSDELAY BEEING TO LA

LCS := MR   
     + /DMA12 * /LUA12 * LCS         ; LCS FROM MR AND UNTIL MA12 HAS GONE HIGH AND
     + DMA12 * LUA12 * LCS           ; I.E. LMA COUNTED FROM 0 to 8K.
     + /DMA12 * LUA12 * LCS


MDLY := CSDLY

DMA12 := LUA12

DMAP := MAP

IF (VCC) SLCOND = ACOND * CSECOND
                + ACOND * CSLOOP


DESCRIPTION



; 270487 : M3202B
; 160687 JLB: DLYO AFTER EVERY MAP.
; 070987 C JLB: SLCOND NEW OUTPUT USED IN 44404