PAL16R4
CJTC 30SEP87
44511A, 26H, LEV0

CLK PIL0 PIL1 PIL2 PIL3 CLK /MREQ /WCA NC9 GND
/OE LEV0 /NC13 /NC14 /NC15 /NC16 CUP /NC18 /CWR VCC

; LEVEL ZERO
IF (VCC) /LEV0  = PIL3
                + PIL2
                + PIL1
                + PIL0

; (CWR)
IF (VCC) CWR = MREQ * WCA   ; SET ON WRITE TO CACHE
             + CWR * /CLK   ; HOLD UNTIL START OF NEXT CYCLE
; CUP
/CUP := /CWR * MREQ         ; CUP := CWR * MREQ ; SET ON WRITE TO CACHE
      + /CUP * /MREQ        ;      + CUP * /MREQ ; HOLD UNTIL NEXT MREQ

DESCRIPTION

; 180587 M3202B

061087 CJTC : ADDED CACHE UPDATE BIT (CUP) FOR M3202D