PAL16L8
ADGD 18/8/86
45008B, 2F, DATA

/MWRITE /SWDIS LBD0 LBD1 LBD3 LBD4 /BIOXL ECCR /BCGNT50R GND
/HIEN /OER /MR /QD /TST /DISB /CLRERR /OET /DIS VCC

IF (VCC) OET = MWRITE                   ;ON WRITE TO MEMORY

IF (VCC) OER = BCGNT50R                 ;ON READ FROM MEMORY AFTER THE ADDRESS PE
             + TST * MWRITE             ;ON WRITE IN TEST MODE BOTH OER AND OET S


IF (VCC) CLRERR = MR                    ;CLEAR PARITY ERROR ON MR, READING EPESL
                + /BCGNT50R             
                + DISB                  
                + QD                    
                                        
IF (VCC) DISB = LBD3 * BIOXL * ECCR     ;SET IF LDB3=1 AND IOX=ECCR
              + /MR * DISB * /BIOXL     ;HOLD UNTIL NEXT IOX=ECCR
              + /MR * DISB * /ECCR      
                                        
IF (VCC) TST = LBD0 * BIOXL * ECCR      ;SET IF ANY OF LBD0,1,4 AND IOX=ECCR
             + LBD1 * BIOXL * ECCR      ;HOLD UNTIL IOX=ECCR
             + LBD4 * BIOXL * ECCR
             + /MR * TST * /BIOXL
             + /MR * TST * /ECCR


IF (VCC) DIS = DISB + SWDIS


DESCRIPTION

; 200387 CJTC: LOGICAL ERRORS IN EQUATIONS FOR DISB AND TST
; 260387 CJTC: CHANGED PIN 2 /EPESL TO /EPEAL - CIRCUIT CHANGE ONLY!!!
; 260387 JLB: CLRERR COMES IMMEDIATELY TO MAKE PERR0&1 PULSES ONLY!!!

; 180587 M3202B
; 091087 B CJTC: AM29833 ARE GIVING ERROR OUTPUT EVEN BEFORE CLOCKED.
;                QD GOES INACTIVE ON 6, JUST BEFORE RDATA THUS STOPPING
;                THE FALSE CLOCKING OF THE 29833 BY HOLDING CLRERR TRUE.