# ND-120 Basys3 - the synthesis source list, read by vivado_build.tcl.
#
# Taken on 30-SEP-2026 from the Basys3 Vivado GUI project (ND3202D.xpr,
# fileset sources_1), IN THE PROJECT'S ORDER: all 267 files it held. Until
# then the list existed only in that project, outside the repository.
#
# One path per line, relative to Verilog/. A line starting with '#' is a
# comment. A line starting with '-' is a file the project held but had
# DISABLED (AutoDisabled=1): its synth_1 run did not read it, so
# vivado_build.tcl does not either - they are listed only so this file
# stays a complete copy of the project's list. The project's own synthesis
# script (ND3202D.runs/synth_1/ND120_TOP.tcl) read the one .vh header first
# and then the 258 enabled .v files in exactly this order; vivado_build.tcl
# does the same.
#
# Adding a file: put it here. The old script's second list (sources it
# added to the project when missing) is gone - every one of those 26 files
# was already in the project, and they are all in this list.

Shared/ndlib/A02.v
Shared/support/AM29833A.v
Shared/support/AM29841.v
Shared/support/AM29861A.v
Shared/support/AM29C821.v
Shared/logisim/AND_GATE.v
Shared/logisim/AND_GATE_3_INPUTS.v
Shared/logisim/AND_GATE_4_INPUTS.v
Shared/logisim/AND_GATE_6_INPUTS.v
Shared/logisim/Adder.v
Shared/support/Am9150.v
Shared/support/nd120_backwiring_defaults.vh
Shared/support/BACKWIRING_PROM.v
CPU-BOARD-3202/circuit/BIF_5.v
CPU-BOARD-3202/circuit/BIF_BCTL_6.v
CPU-BOARD-3202/circuit/BIF_BCTL_BDRV_7.v
CPU-BOARD-3202/circuit/BIF_BCTL_SYNC_8.v
CPU-BOARD-3202/circuit/BIF_DPATH_9.v
CPU-BOARD-3202/circuit/BIF_DPATH_BDLBD_10.v
CPU-BOARD-3202/circuit/BIF_DPATH_CDLBD_11.v
CPU-BOARD-3202/circuit/BIF_DPATH_LDBCTL_12.v
CPU-BOARD-3202/circuit/BIF_DPATH_PESPEA_13.v
CPU-BOARD-3202/circuit/BIF_DPATH_PPNLBD_14.v
DELILAH-CPU/CGA/circuit/BusDriver16.v
DELILAH-CPU/CGA/circuit/CGA.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_ARG.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_DBR.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_GPR.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_OUTMUX.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_OUTMUX_IDBS.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_OUTMUX_SEL8.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_QREG.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_RALU_LOGOP.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_RALU_MUX216L.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_SHIFT.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_SMUX.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_STS.v
DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_SWAP.v
DELILAH-CPU/CGA_ALU/circuit/CGA_CPU_ALU_CONTR.v
DELILAH-CPU/CGA_ALU/circuit/CGA_CPU_ALU_OUTMUX_SEL7.v
DELILAH-CPU/CGA_ALU/circuit/CGA_CPU_ALU_RALU.v
DELILAH-CPU/CGA_ALU/circuit/CGA_CPU_ALU_RMUX.v
DELILAH-CPU/CGA_DCD/circuit/CGA_DCD.v
DELILAH-CPU/CGA_IDBCTL/circuit/CGA_IDBCTL.v
DELILAH-CPU/CGA_IDBCTL/circuit/CGA_IDBCTL_PGSREG.v
DELILAH-CPU/CGA_IDBCTL/circuit/CGA_IDBCTL_SEL6.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_CLR.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_CLR_CLRBIT.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_HIGEL.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_HIRL.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_LOGEL.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_LORL.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_VMUX.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_MASK.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_MASK_MASKBIT.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_MREQ.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_REG.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_REG_RQBIT_V2.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_MDCD.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_CMP.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_CMP_MAGCMP.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_ISMUX.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_OSMUX.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_PTY.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_PTY_PTYENC.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_STAT.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_STAT_SBIT.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_VHR.v
DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_IRSRC.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_ADD.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_AP09.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_APOS_CALCA.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_APOS_INC.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_DECODE.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_FASTADD.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_LA1025.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_LASEL.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_PTSEL.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_SEGPT.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_SEGPT_PCR.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_SEGPT_SEG.v
DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_SEGPT_XPT.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_CONDREG.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_CSEL.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_IINC.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_INCOUNT.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_IPOS.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_MASEL.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_STACK.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_STACK_BIT.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_STACK_BIT12.v
DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_WCAREG.v
DELILAH-CPU/CGA_TESTMUX/circuit/CGA_TESTMUX.v
DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP.v
DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP_BRKDET.v
DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP_TBUF.v
DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP_TVGEN.v
DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP_TVGEN_P2.v
DELILAH-CPU/CGA_WRF/circuit/CGA_WRF.v
DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK.v
DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_DR16.v
DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_LR16.v
DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_PREG.v
DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_SEL16.v
Shared/ndlib/CMP4.v
CPU-BOARD-3202/circuit/CPU_15.v
CPU-BOARD-3202/circuit/CPU_CS_16.v
CPU-BOARD-3202/circuit/CPU_CS_ACAL_17.v
CPU-BOARD-3202/circuit/CPU_CS_CTL_18.v
CPU-BOARD-3202/circuit/CPU_CS_PROM_19.v
CPU-BOARD-3202/circuit/CPU_CS_TCV_20.v
CPU-BOARD-3202/circuit/CPU_CS_WCS_21_22.v
CPU-BOARD-3202/circuit/CPU_MMU_24.v
CPU-BOARD-3202/circuit/CPU_MMU_CACHE_25.v
CPU-BOARD-3202/circuit/CPU_MMU_CSR_26.v
CPU-BOARD-3202/circuit/CPU_MMU_HIT_27.v
CPU-BOARD-3202/circuit/CPU_MMU_PPNX_28.v
CPU-BOARD-3202/circuit/CPU_MMU_PTIDB_30.v
CPU-BOARD-3202/circuit/CPU_MMU_PT_29.v
CPU-BOARD-3202/circuit/CPU_PROC_32.v
CPU-BOARD-3202/circuit/CPU_PROC_CGA_33.v
CPU-BOARD-3202/circuit/CPU_PROC_CMDDEC_34.v
CPU-BOARD-3202/circuit/CYC_36.v
CPU-BOARD-3202/circuit/CYC_CC_D.v
CPU-BOARD-3202/circuit/CYC_TERM_D.v
Shared/logisim/Comparator.v
DECODE-GateArray/DGA/circuit/DECODE_DGA.v
DECODE-GateArray/DGA/circuit/DECODE_DGA_COMM.v
DECODE-GateArray/DGA/circuit/DECODE_DGA_IDBS.v
DECODE-GateArray/DGA/circuit/DECODE_DGA_POW.v
Shared/logisim/D_FLIPFLOP.v
Shared/ndlib/D_FLIPFLOP_EN.v
Shared/logisim/Decoder_8.v
DECODE-GateArray/DGA/circuit/F091.v
DECODE-GateArray/DGA/circuit/F103.v
DECODE-GateArray/DGA/circuit/F571.v
DECODE-GateArray/DGA/circuit/F595.v
DECODE-GateArray/DGA/circuit/F714.v
DECODE-GateArray/DGA/circuit/F924.v
Shared/ndlib/F924_EN.v
Shared/support/FIFO_8BIT.v
Shared/support/IDT6168A_20.v
Shared/support/IMS1403_25.v
CPU-BOARD-3202/circuit/IO_37.v
CPU-BOARD-3202/circuit/IO_DCD_38.v
CPU-BOARD-3202/circuit/IO_PANCAL_40.v
CPU-BOARD-3202/circuit/IO_REG_41.v
CPU-BOARD-3202/circuit/IO_UART_42.v
Shared/logisim/J_K_FLIPFLOP.v
Shared/ndlib/J_K_FLIPFLOP_EN.v
Shared/ndlib/L4.v
Shared/ndlib/L8.v
Shared/ndlib/LATCH.v
Shared/ndlib/M169C.v
Shared/ndlib/M169C_EN.v
CPU-BOARD-3202/circuit/MEM_43.v
CPU-BOARD-3202/circuit/MEM_ADDR_44.v
CPU-BOARD-3202/circuit/MEM_ADEC_45.v
CPU-BOARD-3202/circuit/MEM_DATA_46.v
CPU-BOARD-3202/circuit/MEM_ERROR_47.v
CPU-BOARD-3202/circuit/MEM_LBDIF_48.v
CPU-BOARD-3202/circuit/MEM_RAMC_50.v
CPU-BOARD-3202/circuit/MEM_RAM_49_BLOCKRAM.v
Shared/ndlib/MUX21L.v
Shared/ndlib/MUX21LP.v
Shared/ndlib/MUX24P.v
Shared/ndlib/MUX31LP.v
Shared/ndlib/MUX34P.v
Shared/ndlib/MUX41P.v
Shared/ndlib/MUX81.v
Shared/logisim/Multiplexer_2.v
Shared/logisim/Multiplexer_2_w_enable.v
Shared/logisim/Multiplexer_4.v
Shared/logisim/Multiplexer_8.v
Shared/logisim/Multiplexer_bus_2.v
Shared/logisim/NAND_GATE.v
Shared/logisim/NAND_GATE_3_INPUTS.v
Shared/logisim/NAND_GATE_4_INPUTS.v
Shared/logisim/NAND_GATE_5_INPUTS.v
Shared/logisim/NAND_GATE_6_INPUTS.v
Shared/logisim/NAND_GATE_7_INPUTS.v
Shared/logisim/NAND_GATE_8_INPUTS.v
ND120_CORE.v
CPU-BOARD-3202/circuit/ND3202D.v
Shared/ndlib/ND38GHP.v
Shared/ndlib/ND38GLP.v
Shared/logisim/NOR_GATE.v
Shared/logisim/NOR_GATE_3_INPUTS.v
Shared/logisim/NOR_GATE_4_INPUTS.v
Shared/logisim/OR_GATE.v
Shared/logisim/OR_GATE_3_INPUTS.v
Shared/logisim/OR_GATE_4_INPUTS.v
Shared/logisim/OR_GATE_5_INPUTS.v
Shared/logisim/OR_GATE_6_INPUTS.v
Shared/logisim/OR_GATE_7_INPUTS.v
Shared/logisim/OR_GATE_8_INPUTS.v
PAL/PAL_44302B.v
PAL/PAL_44303B.v
PAL/PAL_44304E.v
PAL/PAL_44305D.v
PAL/PAL_44306A.v
PAL/PAL_44307C.v
PAL/PAL_44310D.v
PAL/PAL_44401B.v
PAL/PAL_44402D.v
PAL/PAL_44402D_EN.v
PAL/PAL_44403C.v
PAL/PAL_44403C_EN.v
PAL/PAL_44404C.v
PAL/PAL_44404C_EN.v
PAL/PAL_44407A.v
PAL/PAL_44407A_EN.v
PAL/PAL_44408B.v
PAL/PAL_44408B_EN.v
CPU-BOARD-3202/circuit/PAL_44445B_D.v
CPU-BOARD-3202/circuit/PAL_44446B_D.v
PAL/PAL_44511A.v
PAL/PAL_44511A_EN.v
PAL/PAL_44601B.v
PAL/PAL_44801A.v
PAL/PAL_44803A.v
PAL/PAL_44902A.v
PAL/PAL_44904B.v
PAL/PAL_45001B.v
PAL/PAL_45008B.v
PAL/PAL_45009B.v
Shared/ndlib/R41P.v
Shared/ndlib/R41P_EN.v
Shared/ndlib/R81.v
Shared/ndlib/R81_EN.v
Shared/ndlib/RMUX_Gates.v
Shared/support/SC2661_UART.v
Shared/ndlib/SCAN_FF.v
Shared/ndlib/SCAN_FF_EN.v
Shared/ndlib/SCAN_WITH_SET_N.v
Shared/ndlib/SCAN_WITH_SET_N_EN.v
Shared/ndlib/SR44.v
Shared/ndlib/SR44_EN.v
Shared/support/SevenSegDebug.v
Shared/support/TMM2018D_25.v
Shared/support/TTL_74139.v
Shared/support/TTL_74244.v
Shared/support/TTL_74245.v
Shared/support/TTL_74273.v
Shared/support/TTL_74374.v
Shared/support/TTL_74534.v
Shared/support/TTL_74646.v
Shared/support/TTL_74648.v
Shared/logisim/XNOR_GATE_ONEHOT.v
Shared/logisim/XOR_GATE_ONEHOT.v
ND120_TOP.v
- PAL/PAL_44445B.v
- PAL/PAL_44446B.v
- DECODE-GateArray/DGA/circuit/F617.v
- Shared/support/TTL_74393.v
- Shared/ndlib/SCAN_WITH_RESET_N_EN.v
- DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_REG_RQBIT.v
- CPU-BOARD-3202/circuit/MEM_RAM_49.v
- Shared/support/SIP1M9.v