DMA High Bits (8-15) Detailed Analysis - The Critical Missing Piece¶

Executive Summary¶

The high 8 bits (8-15) of RRTS and RTTS are DMA module status bits and are CRITICAL for proper SINTRAN operation. These bits are cleared automatically on register read and control DMA completion signaling. Your emulator likely fails because these DMA bits aren't properly generated and cleared.

RRTS High Bits (8-15) - DMA Module Status¶

Bit-by-Bit DMA Analysis (RRTS)¶

Bit	Name	SINTRAN Usage	IRQ Behavior	Clear Behavior
8	BlockEnd	XBLDN test - Controls block processing	Multiple IRQs possible	Cleared on RRTS read
9	FrameEnd	DMA frame completion	Multiple IRQs possible	Cleared on RRTS read
10	ListEnd	DMA list completion	Multiple IRQs possible	Cleared on RRTS read
11	ListEmpty	CRITICAL - Stops receiver	Triggers IRQ	Cleared on RRTS read
12	Reserved	Not used	-	Cleared on RRTS read
13	X21D	X.21 data error	Triggers IRQ	NOT cleared on read
14	X21S	X.21 clear indication	Triggers IRQ	NOT cleared on read
15	ReceiverOverrun	Receiver overrun	Triggers IRQ	NOT cleared on read

Critical DMA Bit Processing in SINTRAN¶

BlockEnd (Bit 8) Processing¶

IF A NBIT XBLDN THEN            % Line 104483 - Check BlockEnd
   IF A = "ERB" THEN GO FAR ZSTARC FI
   GO FAR OUT1
FI

Analysis:

// XBLDN = BlockEnd = bit 8 = 0x0100
if ((rrts & 0x0100) == 0)  // If BlockEnd NOT set
{
    // No more blocks to process - this is NORMAL after packet completion
    if (rrts == ERB_CONSTANT)
    {
        EnableReceiver();
    }
    return;
}
// Continue processing if BlockEnd IS set (more blocks available)

ListEmpty (Bit 11) - Receiver Stopper¶

IF HASTAT/\"EMTY" >< 0 THEN     % Line 104463 - Check ListEmpty
   0=:ACTSW                     % Stop device
   MIN STPCNT                   % Increment counter

Analysis:

// EMTY = ListEmpty = bit 11 = 0x0800
if ((rrts & 0x0800) != 0)  // If ListEmpty set
{
    stopDevice();           // STOPS ALL RECEPTION!
    incrementStopCounter();
    return;  // No more packets processed
}

RTTS High Bits (8-15) - DMA Module Status¶

Bit-by-Bit DMA Analysis (RTTS)¶

Bit	Name	SINTRAN Usage	IRQ Behavior	Clear Behavior
8	BlockEnd	DMA block completion	Multiple IRQs possible	Cleared on RTTS read
9	FrameEnd	DMA frame completion	Multiple IRQs possible	Cleared on RTTS read
10	ListEnd	BSKP test - Skip operation	Single IRQ per list	Cleared on RTTS read
11	TransmissionFinished	Part of SILFO mask	Triggers IRQ	Cleared on RTTS read
12-14	Reserved	Not used	-	Cleared on RTTS read
15	Illegal	SILFO bit - Format error	Triggers IRQ	NOT cleared on read

Critical DMA Bit Processing in SINTRAN¶

ListEnd (Bit 10) Processing¶

BSKP ONE 10 DA                  % Line 51397 - Skip if ListEnd set

Analysis:

// ListEnd = bit 10 = 0x0400
if ((rtts & 0x0400) != 0)  // If ListEnd set
{
    skipNextOperation();    // DMA list complete, skip processing
}

TransmissionFinished (Bit 11) - Success Indicator¶

IF A/\ "SILFO+TXUND" = 0 THEN   % Line 104046 - Check completion

Analysis:

// TransmissionFinished is part of SILFO mask!
// But SILFO = 0x8000 (bit 15), not bit 11!
// This suggests TransmissionFinished is NOT part of the error check

Critical Discovery: DMA Bits Auto-Clear Behavior¶

From C# Documentation Comments:¶

/// Note: Bits 8-15 are cleared when reading the Receiver Transfer Status
/// Note that Transmission Finished (Transmitter Transfer Status, bit 11) always gives a DMA Module Request (bit 4).

SINTRAN Register Read Behavior:¶

RRTS Read Operation:
1. Hardware returns full 16-bit status
2. Bits 8-15 (DMA status) automatically cleared after read
3. Bits 0-7 (data module status) remain until hardware changes them

RTTS Read Operation:  
1. Hardware returns full 16-bit status
2. Bits 8-15 (DMA status) automatically cleared after read  
3. Bits 0-7 (data module status) remain until hardware changes them

IRQ Generation and Bit Relationships¶

Multiple IRQ Sources - OR'ed Together¶

Receiver IRQ (Level 13) Sources:

// Multiple conditions can trigger same interrupt
bool receiverIRQ = 
    (rrts & ReceiverStatusBits.DataAvailable) != 0 ||      // Data ready
    (rrts & ReceiverStatusBits.StatusAvailable) != 0 ||    // Status available
    (rrts & ReceiverStatusBits.DMAModuleRequest) != 0 ||   // DMA request  
    (rrts & ReceiverStatusBits.ListEmpty) != 0 ||          // Buffer exhaustion
    (rrts & ReceiverStatusBits.BlockEnd) != 0 ||           // Block complete
    (rrts & ReceiverStatusBits.FrameEnd) != 0;             // Frame complete

// Signal level 13 IRQ if ANY condition true
if (receiverIRQ)
{
    TriggerInterrupt(13);  // HIINT handler called
}

Transmitter IRQ (Level 12) Sources:

// Multiple conditions can trigger same interrupt  
bool transmitterIRQ =
    (rtts & TransmitterStatusBits.TransmitBufferEmpty) != 0 ||     // Buffer ready
    (rtts & TransmitterStatusBits.TransmitterUnderrun) != 0 ||     // Underrun error
    (rtts & TransmitterStatusBits.DMAModuleRequest) != 0 ||        // DMA request
    (rtts & TransmitterStatusBits.TransmissionFinished) != 0 ||    // TX complete
    (rtts & TransmitterStatusBits.BlockEnd) != 0 ||               // Block complete
    (rtts & TransmitterStatusBits.ListEnd) != 0;                  // List complete

// Signal level 12 IRQ if ANY condition true
if (transmitterIRQ)
{
    TriggerInterrupt(12);  // HOINT handler called
}

The Missing DMA Implementation in Your Emulator¶

Problem: DMA Status Not Generated¶

// Your current implementation (likely):
ReceiverStatusBits rrts = ReceiverStatusBits.DataAvailable;  // 0x0001

// SINTRAN expects DMA completion bits:
ReceiverStatusBits correctRRTS = 
    ReceiverStatusBits.DataAvailable |      // 0x0001 - Data ready
    ReceiverStatusBits.BlockEnd |           // 0x0100 - Block complete  
    ReceiverStatusBits.FrameEnd;            // 0x0200 - Frame complete
// Total: 0x0301

// After RRTS read, bits 8-15 auto-clear:
ReceiverStatusBits afterRead = correctRRTS & 0x00FF;  // 0x0001 (only low bits remain)

Problem: Missing TransmissionFinished¶

// Your current implementation (likely):
TransmitterStatusBits rtts = 0;  // No bits set = success

// SINTRAN expects DMA completion:
TransmitterStatusBits correctRTTS =
    TransmitterStatusBits.TransmissionFinished; // 0x0800 - TX complete

// This triggers interrupt but then auto-clears on read

Correct DMA Emulation Implementation¶

Receiver DMA Status Generation¶

public class HDLCReceiverEmulation
{
    private ReceiverStatusBits currentRRTS = 0;

    public void OnPacketReceived(byte[] packet)
    {
        // Set DMA completion status
        currentRRTS = 
            ReceiverStatusBits.DataAvailable |      // Packet ready
            ReceiverStatusBits.StatusAvailable |    // Status ready  
            ReceiverStatusBits.BlockEnd |           // DMA block complete
            ReceiverStatusBits.FrameEnd;            // DMA frame complete

        // Do NOT set ListEmpty unless actually out of buffers
        // Do NOT set X.21 errors unless protocol error

        TriggerInterrupt(13);  // HIINT
    }

    public ReceiverStatusBits ReadRRTS()
    {
        ReceiverStatusBits result = currentRRTS;

        // Auto-clear DMA bits (8-15) after read
        currentRRTS &= (ReceiverStatusBits)0x00FF;

        return result;
    }

    public void OnReceiveBuffersEmpty()
    {
        // Only set when actually out of buffers
        currentRRTS |= ReceiverStatusBits.ListEmpty;  // Stops receiver
        TriggerInterrupt(13);
    }
}

Transmitter DMA Status Generation¶

public class HDLCTransmitterEmulation
{
    private TransmitterStatusBits currentRTTS = 0;

    public void OnTransmissionComplete(bool success)
    {
        if (success)
        {
            // Set completion status for successful transmission
            currentRTTS = TransmitterStatusBits.TransmissionFinished;  // 0x0800

            // Do NOT set error bits (TransmitterUnderrun, Illegal)
        }
        else
        {
            // Set error status  
            currentRTTS = TransmitterStatusBits.TransmitterUnderrun;   // 0x0002
        }

        TriggerInterrupt(12);  // HOINT
    }

    public TransmitterStatusBits ReadRTTS()
    {
        TransmitterStatusBits result = currentRTTS;

        // Auto-clear DMA bits (8-15) after read
        currentRTTS &= (TransmitterStatusBits)0x00FF;

        return result;
    }

    public void OnTransmitListComplete()
    {
        currentRTTS |= TransmitterStatusBits.ListEnd;  // 0x0400
        TriggerInterrupt(12);
    }
}

Testing DMA Bit Behavior¶

Verify Auto-Clear Functionality¶

public void TestDMABitClearing()
{
    // Set DMA status bits
    TransmitterStatusBits rtts = TransmitterStatusBits.TransmissionFinished;  // 0x0800
    Console.WriteLine($"Before read: RTTS = 0x{(int)rtts:X4}");

    // Simulate SINTRAN read
    TransmitterStatusBits firstRead = ReadRTTS();   // Should return 0x0800
    Console.WriteLine($"First read: 0x{(int)firstRead:X4}");

    TransmitterStatusBits secondRead = ReadRTTS();  // Should return 0x0000  
    Console.WriteLine($"Second read: 0x{(int)secondRead:X4}");

    // Verify behavior matches SINTRAN expectations
    Debug.Assert((int)firstRead == 0x0800, "First read should show DMA bits");
    Debug.Assert((int)secondRead == 0x0000, "Second read should clear DMA bits");
}

Summary: The Root Cause¶

Your HDLC emulator fails because:

Missing DMA completion bits (BlockEnd, FrameEnd, TransmissionFinished)
No auto-clear behavior on register reads
Incorrect IRQ generation - multiple sources not properly OR'ed
Wrong success signaling - SINTRAN expects TransmissionFinished bit, then auto-clear

The fix: - Generate proper DMA status bits (8-15) when operations complete - Implement auto-clear behavior on RRTS/RTTS reads - Set TransmissionFinished (bit 11) for successful transmission - Set BlockEnd/FrameEnd for packet completion - Only set ListEmpty when actually out of buffers

Your bit interpretations are correct - the issue is generating the right bit patterns at the right times with proper clearing behavior!

Updated with Complete Enable Bit Analysis¶

Combined DMA Setup Requirements:¶

Transmitter Enable (WTTC) - Must Set: - EnableTransmitterDMA (bit 3) - MANDATORY for DMA operation - TransmitterEnabled (bit 2) - MANDATORY for physical transmission
- DMAModuleIE (bit 4) - For DMA interrupt generation - RequestToSend (bit 6) - For modem handshaking

Receiver Enable (WRTC) - Must Set: - EnableReceiverDMA (bit 3) - MANDATORY for DMA operation - EnableReceiver (bit 2) - MANDATORY for physical reception - DMAModuleIE (bit 4) - For DMA interrupt generation
- DTR (bit 6) - For modem connection (almost always active)

SINTRAN DMA Configuration Patterns:¶

TX: 105 (standard), 107 (with underrun), 134 (X.21)
RX: 304 (basic + modem), 305 (full interrupts)

Critical: Both TX and RX must have their respective DMA enable bits (bit 3) set, plus appropriate interrupt enable bits (bit 4) for the complete DMA interrupt generation and auto-clearing behavior to work correctly.

The documents Transmitter_Enable_Bits_Analysis.md and Receiver_Enable_Bits_Analysis.md contain the complete SINTRAN usage patterns and exact bit configurations needed.