Deep Analysis: Packet Setup Before HDLC DMA Transmission¶

Overview¶

This document analyzes how SINTRAN prepares packets for transmission before handing them to the HDLC DMA controller. Based on source code analysis around line 103046+ in s3vs-4-L-RONNY.symb, SINTRAN follows a sophisticated multi-step process to convert user data into DMA-ready transmission buffers.

Transmission Flow: User → SINTRAN → DMA → HDLC Hardware¶

User Process Request
    ↓ (System call)
SINTRAN OS Message Processing  
    ↓ (Buffer allocation)
DMA Descriptor Setup
    ↓ (LKEY with COM5025 control bits)
Data Copy to DMA Buffer
    ↓ (Physical memory operations)
HDLC DMA Controller Start
    ↓ (WDMA, WDCR register operations)
COM5025 Chip Transmission
    ↓ (TSOM, data, TEOM sequence)
Physical Line Output

Phase 1: User Message Reception and Validation¶

User Request Processing (Line 103046+):¶

% SINTRAN receives transmission request from user process
HANDLE_USER_TX_REQUEST:
    A:=RSCUR=:X                           % Get user request context

    % Message validation - CRITICAL size checks
    IF MESSM + 1 < 0 THEN                 % Validate message length  
        1=:MESSM                          % Force positive value
    FI

    % Extract message parameters
    A:=RSCUR                              % User data pointer
    MESSM=:MESSAGE_LENGTH                 % Get actual data length
    MESSID=:MESSAGE_ID                    % Unique message identifier

Size Validation Logic:¶

% Based on PROCPKT reverse analysis - transmission has same limits:
IF MESSAGE_LENGTH < 7 THEN              % Minimum HDLC frame size
   A:=EILFZ                             % Error: Illegal frame size
   GO ERROR_RETURN
FI

IF MESSAGE_LENGTH > MAXR THEN           % Maximum frame size (MAXR constant)
   A:=EILSIZ                            % Error: Too large  
   GO ERROR_RETURN
FI

Phase 2: DMA Buffer Allocation and Management¶

Buffer Acquisition:¶

% SINTRAN allocates DMA buffers for transmission
ALLOCATE_TX_BUFFERS:
    CALL GET_DMA_BUFFER                  % Get free DMA buffer from pool
    IF BUFFER_UNAVAILABLE THEN
        A:=ENOBF                         % Error: No buffers available
        GO RETRY_OR_ERROR
    FI

    % Set up buffer parameters
    BUFFER_ADDRESS=:DDD2                 % Physical buffer address
    BUFFER_SIZE=:DDD3                    % Available buffer space
    USER_DATA_LENGTH=:DDD4               % Actual data to transmit

Buffer Space Calculation:¶

% Account for HDLC frame overhead and displacement
EFFECTIVE_BUFFER_SIZE = BUFFER_SIZE - DISP1 - HDLC_OVERHEAD
% DISP1 = Displacement (header space reserved)  
% HDLC_OVERHEAD = FCS, flags, etc.

IF USER_DATA_LENGTH > EFFECTIVE_BUFFER_SIZE THEN
    % Multi-buffer transmission required
    SETUP_MULTI_BUFFER_CHAIN()
FI

Phase 3: DMA Descriptor Construction (CRITICAL)¶

Single Frame Descriptor Setup (Line 103667+):¶

% Based on actual SINTRAN patterns found:
SETUP_DMA_DESCRIPTOR:
    % Calculate addresses
    A:=OMSG+CHEAD=:X.LMEM2=:D           % Set buffer address (low word)
    T:=MASTB=:X.LMEM1                   % Set physical bank (high word)

    % Set byte count  
    A-DISP1=:LIINT.LBYTC                % Set data length minus displacement

    % CRITICAL: Set LKEY with COM5025 control bits
    FSERM=:X.LKEY                       % FSERM = 002003₈ = Single frame control

    % FSERM breakdown:
    % 002003₈ = 0000 1000 0000 0011
    %          ├─ 010: Block to be transmitted  
    %          └─ 003: COM5025 TSOM(1) + TEOM(1) = complete frame

    D=:X                                % Store descriptor address

Multi-Frame Descriptor Chain Setup:¶

% For packets requiring multiple DMA buffers:
SETUP_MULTI_BUFFER_CHAIN:
    % First descriptor - Start of Message
    FirstBlock = 002001₈=:X1.LKEY       % Block + TSOM only
    FIRST_BUFFER_ADDR=:X1.LMEM2
    MASTB=:X1.LMEM1  
    FIRST_CHUNK_SIZE=:X1.LBYTC

    % Middle descriptors - Data continuation
    WHILE MORE_DATA_CHUNKS DO
        MiddleBlock = 002000₈=:Xi.LKEY   % Block only, no flags
        CHUNK_BUFFER_ADDR=:Xi.LMEM2
        MASTB=:Xi.LMEM1
        CHUNK_SIZE=:Xi.LBYTC
        ADVANCE_TO_NEXT_DESCRIPTOR()
    DONE

    % Final descriptor - End of Message
    LastBlock = 002002₈=:Xn.LKEY        % Block + TEOM only  
    FINAL_BUFFER_ADDR=:Xn.LMEM2
    MASTB=:Xn.LMEM1
    FINAL_CHUNK_SIZE=:Xn.LBYTC

Phase 4: Data Copy Operations (Line 103075)¶

Physical Memory Copy:¶

% Copy user data to DMA buffer - CRITICAL operation
DATA_COPY_TO_DMA_BUFFER:
    DDD2=:XXUBF                         % Set user buffer address  
    T:=DDD3=:D                          % Set data length
    X+BHEAD=:XXSBF                      % Set DMA buffer + header offset

    CALL Z0PHY                          % *** COPY USER DATA TO DMA BUFFER ***
    *IOF                                % Complete physical copy operation

Memory Bank Management:¶

% SINTRAN handles memory bank switching during copy:
Z0PHY_BANK_SWITCHING:
    SAVE_CURRENT_BANK()                 % Preserve current memory context
    SET_SOURCE_BANK(USER_BANK)          % Switch to user data bank
    SET_DEST_BANK(DMA_BANK)             % Switch to DMA buffer bank

    PERFORM_BYTE_COPY(length)           % Copy data byte by byte

    RESTORE_ORIGINAL_BANK()             % Restore memory context

Phase 5: Message Queue Integration (Line 103077)¶

Message Chain Setup:¶

% Link transmission request into system queues
MESSAGE_QUEUE_SETUP:
    X:=RSCUR                            % Get user request context  
    CALL ICHAIN                         % Link into internal message chain
    *ION                                % Enable interrupts

    % Set up message control block
    T:=MASTB                            % Set memory bank reference
    BBID@3 STATX                        % Set buffer ID for tracking
    BMBYT@3 STATX                       % Set maximum byte count
    BBYTC@3 STATX                       % Set actual byte count
    XCHAI@3 STATX                       % Set up chain pointers

Queue Management:¶

% OCHAIN pattern indicates queuing to transmission system:
QUEUE_FOR_TRANSMISSION:
    "OCHAIN"                            % Queue message for processing
    XCHAI@3 STATX                       % Set chain management

    % This leads to eventual CALL XHMST (start transmitter DMA)

Phase 6: Device Activation and DMA Start¶

Device State Management:¶

% Activate HDLC transmission (from XHMST analysis):
ACTIVATE_HDLC_TRANSMITTER:
    % Set up DMA address
    LIINT+DPITPHYS;                     % Calculate physical DMA list address
    T:=HDEV+WDMA; *IOF; EXR ST          % Write DMA address to hardware

    % Start DMA with command
    A:=2000\/D; T+"WDCR-WDMA"; *EXR ST  % Start transmitter DMA
    % 2000₈ = 0x400 = Start transmitter command

    % Enable transmission control
    1134+CMODI; T:=HDEV+WTTC; *EXR ST   % Enable transmitter with DMA mode

    % Mark device active
    1 =: ACTSW                          % Set activity switch
    OMSG =: DCBX                        % Set current device control block

Memory Layout and Data Structures¶

DMA Descriptor Structure:¶

DMA Descriptor (4 words):
Word 0: LKEY  = Control + COM5025 bits
Word 1: LBYTC = Byte count  
Word 2: LMEM1 = Memory bank (address high)
Word 3: LMEM2 = Buffer address (address low)

Buffer Layout:¶

DMA Buffer Structure:
Bytes 0-(DISP1-1):     Header space (reserved)
Bytes DISP1-N:         User packet data
Bytes (N+1)-End:       Trailer space (FCS, padding)

Message Control Block:¶

SINTRAN Message Structure:
MESSID:    Message identifier
MESSM:     Message length
RSCUR:     User context pointer
MASTB:     Memory bank reference
BBID:      Buffer identifier  
BMBYT:     Maximum byte count
BBYTC:     Actual byte count
XCHAI:     Chain pointer

Error Handling and Recovery¶

Validation Failures:¶

ERROR_HANDLING:
    % Size validation errors
    EILFZ:  A:=ILLEGAL_FRAME_SIZE_ERROR
    EILSIZ: A:=FRAME_TOO_LARGE_ERROR

    % Resource allocation errors  
    ENOBF:  A:=NO_BUFFERS_AVAILABLE_ERROR

    % Memory operation errors
    ECOPY:  A:=DATA_COPY_FAILURE_ERROR

    % All errors go through:
    CALL SCRET                          % Set error return code
    CALL SADTS                          % Log error status
    GO ERROR_RETURN_TO_USER

Buffer Management Errors:¶

DMA buffer exhaustion: Queue request for later processing
Memory bank conflicts: Retry with different memory allocation
Copy operation failures: Report error to user application

Performance Optimizations¶

Buffer Pool Management:¶

Pre-allocated buffers: DMA buffers allocated at system startup
Buffer recycling: Completed transmission buffers returned to pool
Size optimization: Buffer sizes tuned for common packet sizes

Memory Copy Efficiency:¶

Bank switching minimization: Batch operations when possible
Direct memory access: Bypass unnecessary memory mappings
Cache management: Ensure coherency for DMA operations

Integration with HOINT Interrupt Handler¶

Transmission Completion Flow:¶

1. User calls SINTRAN transmission API
2. SINTRAN sets up DMA descriptors (this analysis)
3. XHMST starts DMA transmission
4. COM5025 chip processes TSOM/data/TEOM sequence  
5. Hardware generates interrupt on completion
6. HOINT reads RTTS status
7. HOINT checks (RTTS & 0x8002) for success/failure
8. HOINT calls NEXTS for next transmission or error handling

Key Constants and Values¶

Critical SINTRAN Constants:¶

FSERM   = 002003₈  % Single frame transmission key
DISP1   = ?        % Header displacement (varies by configuration)  
MAXR    = ?        % Maximum frame size (system dependent)
MASTB   = ?        % Memory bank reference (hardware dependent)
DPITPHYS= ?        % Physical address translation offset

COM5025 Control Bit Patterns:¶

TSOM_ONLY = 001₈   % Start of message flag only (first block)
TEOM_ONLY = 002₈   % End of message flag only (last block)  
BOTH_FLAGS= 003₈   % Both TSOM+TEOM (single block frame)
NO_FLAGS  = 000₈   % Neither flag (middle blocks)

Conclusion¶

SINTRAN's packet setup process is highly sophisticated, involving:

User request validation with size and parameter checking
Dynamic buffer allocation from DMA buffer pools
Explicit COM5025 control programming via LKEY field bits 7-0
Multi-buffer frame support with proper TSOM/TEOM sequencing
Physical memory management with bank switching and address translation
Message queue integration for system-wide coordination
Comprehensive error handling with detailed error codes

The LKEY field containing COM5025 register values is the breakthrough that explains how SINTRAN achieves precise control over HDLC frame boundaries. This architecture enables: - Explicit frame control (no guesswork about TSOM/TEOM) - Multi-block frame support (large packets spanning buffers) - Hardware integration (direct COM5025 chip programming) - Error isolation (validation before hardware submission)

This design demonstrates why SINTRAN's HDLC implementation is robust and reliable - every aspect of packet preparation is explicit and validated before hardware processing begins.