PAL transcription audit - complete sweep, 30-JUL-2026¶
Every hand-converted PAL in Verilog/PAL/ (30 files incl. variants and the two
in-module mirrors) was diffed equation-by-equation against its original PALASM
source in DesignDocuments/PAL-Code/SRC/ (26 sources), by three parallel
read-only audit agents calibrated on the three previously confirmed
transcription bugs (44306A EIPL, 45001B SPEA/SPES, 44801A IOD). Every
suspicious polarity was cross-checked against the actual board instantiation.
The audit itself applied no fixes. Status 28-SEP-2026: all five DIFFs below are
now FIXED in the RTL - each fix carries a "30-JUL audit" comment in the PAL
file. The sections below keep what each error was and what it broke.
Verdict table (all 26 PALs)¶
| PAL | Verdict | Note |
|---|---|---|
| 44302B | DIFF -> FIXED | DSTB: 3 literals inverted in the non-IOX read-strobe term (PAL_44302B.v:104) |
| 44303B | MATCH | |
| 44304E | MATCH | documented adaptations only (TEST removed, APR delay collapsed) |
| 44305D | MATCH | |
| 44306A | MATCH | 29-JUL EIPL fix verified exact; all other equations clean |
| 44307C | MATCH | |
| 44310D | DIFF -> FIXED | BDRY: De Morgan error in hold/clear (both latch+FF branches, PAL_44310D.v:82,102) |
| 44401B | MATCH | benign OE-feedback quirk (OE tied 0 on board) |
| 44402D | DIFF -> FIXED | used-bit loop has odd inversion count vs PALASM pin semantics (PAL_44402D.v:97) |
| 44403C | DIFF -> FIXED | DLY0: 3 wrong literals (MDLY inverted, XOR->XNOR, MAP for DMAP) (PAL_44403C.v:115, _EN.v:109) |
| 44404C | MATCH | C-rev; board was rev D, DLSHADOW addition is an in-file-documented guess (no D source) |
| 44407A | MATCH | incl. _EN |
| 44408B | MATCH | incl. _EN; RT_n=1 placeholder for unsourced 44608A documented in-file |
| 44445B | MATCH | incl. board-local _D clock-enable mirror |
| 44446B | MATCH | incl. _D mirror |
| 44465B | N-A | 6MB variant, deliberately no Verilog (board is 4MB) |
| 44466B | N-A | 6MB variant, deliberately no Verilog |
| 44511A | MATCH | incl. _EN; 26-JUL CUP fix in place; CWR FF adaptation boolean-equivalent |
| 44601B | MATCH | incl. the CYC_CC_D / CYC_TERM_D in-module mirrors |
| 44801A | MATCH | all three 20-JUL fixes verified present |
| 44803A | MATCH | |
| 44902A | MATCH | |
| 44904B | MATCH | cosmetic comment-label swap Q5/Q6/Q7 only |
| 45001B | MATCH | 29-JUL SPEA/SPES fixes verified exact incl. both ifdef branches |
| 45008B | DIFF -> FIXED | DISB + TST hold/clear: OR-for-AND (both), TST also BIOXL polarity (PAL_45008B.v:97-126; first reverted 30-JUL, re-applied later - see section 5) |
| 45009B | MATCH | TEST-mode tri-state ignored, benign (TEST=PD4=0) |
Five PALs had confirmed transcription errors (on top of the three already fixed before the audit). All five are fixed now. Details, ranked by the impact expected at the time:
1. 44403C (UCYIN0) DLY0 - microcycle length decision effectively stuck¶
Verilog/PAL/PAL_44403C.v:115-121 (+ identical in PAL_44403C_EN.v:109-115)
vs SRC/44403C.txt:10-16. Three independent literal errors in the DLY0 sum:
- MDLY_n used where PALASM has asserted MDLY (registered feedback).
- LUA12 XOR DMA12 transcribed as XNOR (both literals inverted) - fires when
LUA12 is STABLE (almost always) instead of for one clock after it changes.
- raw input MAP used where the registered one-clock-delayed DMAP belongs
(the term is even commented "// DMAP").
Impact: DLY0 asserted essentially continuously -> the cycle FSM (PAL_44601B I1,
CYC_TERM_D in CYC_36.v:212,388) likely takes the DELAYED microcycle path every
cycle. Invisible-but-slow in zero-delay Verilator; wrong for cycle fidelity on
silicon. PLAUSIBLY RELATED to the global "everything is slow on the Tang"
observations (Issue E family) - measurable speedup candidate.
2. 44402D (UBITS) - cache used-bit loop polarity broken¶
Verilog/PAL/PAL_44402D.v:83-101 (+_EN) vs SRC/44402D.txt:22-25. The 16R4
registers invert onto the pin (/NUBI := sum -> pin = NOT sum); the Verilog
registers the sum itself and exports it as NUBI_n/NUBD_n = complement of
the physical pin. Board loop (CPU_MMU_CACHE_25.v:235-263) wires it straight
through the NON-inverting Am9150 used-bit RAM back into OUBI/OUBD -> odd
inversion count. Concrete effect: the NUBD "hold during fetch" rule becomes a
TOGGLE-every-fetch; IHIT/USED computed from inverted used bits. At the time of
the audit the cache had never been functionally validated - this was a prime
reason it never could be. (Since 31-AUG-2026 all 8 cache tests pass on the
Nexys board - see CACHE-STATUS.md.)
Also noted: Am9150.v ignores RESET_n (cache-clear s_cclr_n is a no-op in sim).
3. 44310D (LBDIF) BDRY - handshake hold lost (De Morgan)¶
Verilog/PAL/PAL_44310D.v:82-85 (latch) and 99-101 (FF) vs SRC/44310D.txt:14-15.
Clear condition ORs the negated hold terms (clears when EITHER hold term is
false) instead of ANDing them (clear only when BOTH fail). In a DMA memory
cycle BIOXE is off -> the memory hold NEVER holds; symmetrically for IOX.
The PAL's own 1986 errata describes the failure shape of a lost BDRY
("SINTRAN STOPS ON LEVEL 14 DURING STARTUP"). Affects the ND-bus data-ready
handshake out of MEM_LBDIF_48.v.
4. 44302B (LDBCTL) DSTB - bus-read data strobe in the wrong window¶
Verilog/PAL/PAL_44302B.v:104-109 vs SRC/44302B.txt:19-20. The non-IOX term
CACT * /BDRY50 * /BDRY25 * /IORQ was transcribed with ALL THREE bus literals
un-negated (CACT & BDRY50 & BDRY25 & IORQ). Original behavior: DSTB spans
from CACT until BDRY arrives, its rising edge samples CPU-from-bus read data
into the CD/LBD 74646s AT BDRY. As transcribed: the term never fires for a
non-IOX bus read, and a phantom IOX+BDRY window exists.
COUPLING NOTE: BIF_DPATH_CDLBD_11.v picked its FF-mode capture mode
("mode 3", follow-while-low) while DSTB was still wrong. It is still mode 3
with the fixed DSTB; any later change to either must re-validate both
(sim gates test-cdlbd etc.).
5. 45008B (UDATA) DISB + TST - fixed (after one revert)¶
The equation fix was first applied on 30-JUL and REVERTED the same day: with TST
able to hold, CONFIGURE's memory-type probe ran its block write with TST=1, and
OER = BCGNT50R + TST*MWRITE enabled the AM29833 drivers (MEM_DATA_46.v
CHIP_1H/2H) onto LBD during the write - a deliberate loopback on real hardware,
a bus fight in our LBD merge. CONFIGURE crashed to OPCOM and left TST latched.
The corrected equations are in PAL_45008B.v now (both the latch and the FF
branch); they came back in the squashed commit 202c606 (25-AUG-2026). The
exact re-apply date, and whether the LBD merge was changed to handle the
loopback at the same time, are not recorded.
(original finding, for the record)¶
Verilog/PAL/PAL_45008B.v:97/114 (DISB), 102/119 (TST) vs SRC/45008B.txt:19-27.
Same OR-for-AND clear-condition shape as 44310D in BOTH equations; TST
additionally uses BIOXL where the PALASM hold term is /BIOXL. Correct
clear for both = MR | (BIOXL & ECCR) (master reset or the next IOX to ECCR).
As transcribed, DISB drops on any IOX anywhere, TST degenerates to a pulse
inside its own setting IOX. Affects memory/ECC diagnostics (parity-disable,
test-mode read-back via OER) - directly in the Issue G / CONFIGURE-ECC
neighborhood: TST/DISB persistence is exactly what an ECCR-probing diagnostic
manipulates. Dormant in normal boots.
Benign notes (no action needed)¶
- OE-gated feedback pattern (44801A/44803A/44902A/44904B/44511A/44401B): reads fed-back outputs through the OE gate instead of the raw register - benign because every such OE is tied to PD1-PD4 = constant 0 on ND3202D.v:528-531.
- 45009B ignores PALASM TEST-mode output enables (TEST=PD4=0, benign, commented).
- 44904B port-comment labels Q5/Q6/Q7 swapped (comments only).
- 44601B
CC1_reg <= | (...)leading unary reduction-OR - parses identically. - SRC/44803A.txt pin-list typo (
/CSEM /CSEMfor/BSEM /CSEM) - source doc only, equations disambiguate.
The full per-PAL audit reports were session notes and are not kept.