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Module hierarchy

What sits inside what, for every build top. Each top was elaborated with the file list, defines and include folders its own build uses, so ifdefs, generate blocks and parameters are already applied. Every module links to its page; the full list is in MODULES.md.

How to read the trees:

  • Click a module with a triangle to fold its contents in or out. The top two levels start open.
  • name after a module is the instance name in its parent.
  • A module that one parent uses several times goes on one line: x16 and the instance names. What is inside it is drawn once, under that line.
  • A sub-tree is drawn in full the first time it appears on this page. Later copies that are exactly the same (same modules, same instance names, all the way down) say "same as above" and link to it, also across boards.
  • "vendor" marks a part that is not ours and is not followed: FPGA primitives, PLLs, vendor IP, and the MiSTer and MEGA65 frameworks. For MiSTer and MEGA65 the tree starts at our top below the framework.
  • ROM/RAM init files do not change which instances exist, so yosys was given empty stand-ins for them.
Top Module Elaborated Our modules Instances Depth
Simulation (Verilator) ND120_TOP yes 261 2906 13
Tang Nano 20K ND120_TANG20K_TOP yes 262 2904 13
Nexys 4 DDR nd120_nexys4ddr_top yes 287 2943 13
MiSTer emu yes 277 2877 13
MEGA65 R4 R5 R6 nd120_mega65_machine yes 277 2880 13
MEGA65 R3 nd120_mega65_machine yes 277 2880 13
QMTECH XC7A35T nd120_qmtech_top yes 263 2914 13
Basys3 ND120_TOP yes 244 2844 13
Cmod A7-35T nd120_cmod_top yes 245 2845 14

Simulation (Verilator)

Build: Verilog/runSim/Makefile, default settings (make compile: USE_LATCHES=0, VERILOG_TAPE=1, SD_STORAGE=1, CACHE=1).

Defines: VERILATOR_SIM, FPGA_FF_MODE, ND_SDRAM_PACK16, ND120_VERILOG_DEVICES, ND120_SD_STORAGE, ND120_SD_CARD_IMG="../SD-FAT/sim/nd_boot_card.img".

The simulation models in SD-FAT/sim/ are behavioural test models yosys cannot elaborate ($random, file I/O); they contain no module instances and were read as black boxes (their own port list, empty body).

261 of our modules, 2906 module instances, 13 levels deep. Vendor parts: none.

Tang Nano 20K

Build: Verilog/fpga/tang-nano-20k/Makefile (the OSS yosys flow, default VARIANT=slow, CACHE=0); its file list is nd120_tang20k.gprj, the same list the Gowin build reads.

262 of our modules, 2904 module instances, 13 levels deep. Vendor parts: rPLL.

Nexys 4 DDR

Build: Verilog/fpga/nexys4ddr/build.tcl, default arguments.

Defines: TARGET_NEXYS4DDR, FPGA_FF_MODE, MAIN_RAM_DDR2, ND120_N4DDR_MMCM_DIV=60.0, BOARD_CLK_FREQ=16666667, UART_BAUD_RATE=115200, SKIP_WCS_LOAD, ND120_PANEL_CLOCK, ND120_CONSOLE_VGA, ND120_CONSOLE_BAUD=115200, ND120_MIPS_TAP.

287 of our modules, 2943 module instances, 13 levels deep. Vendor parts: BUFG, BUFGMUX_CTRL, MMCME2_BASE, ddr.

MiSTer

Build: Verilog/fpga/mister/nd120.qsf (which sources files.qip). The Quartus top is the framework's sys_top; the tree starts at the core's emu below it.

Defines: FPGA_FF_MODE=1, BOARD_CLK_FREQ=20000000, UART_BAUD_RATE=115200, ND120_UART_DELAY_FRAMES=173, MAIN_RAM_SDRAM=1, ND_SDRAM_PACK16=1, ND_SDRAM_DQ16=1, ND_SDRAM_REFRESH_US=7, QUARTUS_RAM_INFER=1, ND120_PANEL_CLOCK=1, ND120_MIPS_TAP=1, ND120_NO_CACHE=1, SKIP_WCS_LOAD=1, QUARTUS_LATCH_RENAME=1.

build_id.v is written by the build just before synthesis; a stand-in with the same kind of content was used.

The SystemVerilog top was read by the yosys slang plugin (yosys' own reader cannot pass the unpacked arrays in it to hps_io). The modules it instantiates were given to slang as black boxes made from their own headers, then replaced by the real files, which yosys elaborated as for every other top. Framework and vendor parts stay black boxes.

Not followed (framework): 3 file(s).

277 of our modules, 2877 module instances, 13 levels deep. Vendor parts: altera_pll.

MEGA65 R4 R5 R6

Build: Verilog/fpga/mega65/build.tcl board=r6. R4 and R5 build the same Verilog with the same defines (only the VHDL framework top differs). The Vivado top is the framework's mega65_r6; the tree starts at nd120_mega65_machine, which the VHDL CORE/vhdl/main.vhd instantiates as i_machine.

Defines: FPGA_FF_MODE, BOARD_CLK_FREQ=20000000, UART_BAUD_RATE=115200, SKIP_WCS_LOAD, ND120_MIPS_TAP, ND120_PANEL_CLOCK, MAIN_RAM_SDRAM, ND_SDRAM_PACK16, ND_SDRAM_DQ16, ND_SDRAM_REFRESH_US=7.

Not followed (framework): 7 file(s).

277 of our modules, 2880 module instances, 13 levels deep. Vendor parts: none.

MEGA65 R3

Build: Verilog/fpga/mega65/build.tcl board=r3 (HyperRAM instead of SDRAM). The tree starts at nd120_mega65_machine, below the VHDL framework.

Defines: FPGA_FF_MODE, BOARD_CLK_FREQ=13333333, UART_BAUD_RATE=115200, SKIP_WCS_LOAD, ND120_MIPS_TAP, ND120_PANEL_CLOCK, MAIN_RAM_DDR2.

Not followed (framework): 7 file(s).

277 of our modules, 2880 module instances, 13 levels deep. Vendor parts: none.

QMTECH XC7A35T

Build: Verilog/fpga/qmtech-a35t/build.tcl, default arguments.

Defines: FPGA_FF_MODE, MAIN_RAM_SDRAM, ND_SDRAM_PACK16, ND_SDRAM_DQ16, ND_SDRAM_REFRESH_US=7, ND_STORAGE_NO_CACHE, ND_STORAGE_DISCS_UNCACHED, SDFAT_NO_LFN, ND120_PANEL_CLOCK, BOARD_CLK_FREQ=20000000, UART_BAUD_RATE=115200, SKIP_WCS_LOAD.

263 of our modules, 2914 module instances, 13 levels deep. Vendor parts: BUFG, MMCME2_BASE.

Basys3

Build: Verilog/fpga/basys3/vivado_build.tcl with full_synth. Its file list is nd120_basys3_sources.txt next to it (a non-project flow since 30-SEP-2026).

Defines: FPGA_FF_MODE, SKIP_WCS_LOAD, MAIN_RAM_BLOCKRAM, BOARD_CLK_FREQ=16666667, UART_BAUD_RATE=9600.

244 of our modules, 2844 module instances, 13 levels deep. Vendor parts: BUFG, MMCME2_BASE.

Cmod A7-35T

Build: Verilog/fpga/cmod-a7-35t/build.tcl, default arguments.

Defines: TARGET_CMOD_A7, FPGA_FF_MODE, MAIN_RAM_BLOCKRAM, BOARD_CLK_FREQ=27000000, UART_BAUD_RATE=115200, SKIP_WCS_LOAD.

245 of our modules, 2845 module instances, 14 levels deep. Vendor parts: BUFG, MMCME2_BASE.