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Verilog/docs - index

Design notes, references, open plans and solved-problem write-ups for the ND-120 Verilog work. Every tracked file in this folder is listed below once. Links are relative to this folder (repo-root path Verilog/docs/<file>).

The one-line hooks say what each file is for. They are not a re-check of its claims: open the file, and trust the RTL and the cited manuals over any summary. Finished work is kept only as a short root-cause record; the full history of any deleted handoff or plan is in git.

Start here

  • nd120-facts.md - the machine invariants that keep getting re-derived (address spaces, console registers, interrupt sources, WCS layout, board differences, software behaviour), each with its source.
  • build-defines.md - every build option: Verilog defines, sim make variables, per-board build arguments (Nexys, Tang, Basys3, MiSTer, MEGA65, QMTECH, Cmod A7), runSim environment variables.
  • PREREQUISITES.md - every tool the repo needs, how to install it and how to check it.
  • RETRACTED.md - claims that were believed and then disproved; read before trusting an old doc or code comment.
  • SIGNALS.md - evidence-tagged dictionary of the cycle and control-store signals (what each is, who drives it, how we know).

Bus protocol - IOX / IDENT / DMA

  • nd100-bus-deck.pptx - 16-slide deck covering all bus phases: IOX read/write, IDENT poll, DMA read/write, the recovery gap, and CPU-vs-DMA arbitration. Verbatim ND-06.016.01 manual text on each slide; the timing waveforms are drawn reconstructions - trust the RTL and the manual over the drawing.
  • nd100-bus-dma.md - the ND-100 bus and DMA spec from ND-06.016.01 (section 10.8 is the BREQ lifecycle). Read before touching ../ND-BUS-DEVICES/DMA/circuit/ND_DMA_MASTER.v.
  • device-address-map.md - base address, ident and interrupt level of every Verilog ND-bus device.
  • nd100x-device-semantics.md - nd100x device semantics (interrupts, IDENT, floppy, SMD) used as a first reference for the Verilog devices.

Device READMEs and validation plans that build on the above: ../ND-BUS-DEVICES/README.md, ../floppyTester/PLAN-P3-dma-master-validation.md, ../floppyTester/CONFORMANCE.md.

Storage - SD card, floppy, SMD, Winchester, tape

CPU - microcode, instructions, interrupts

Clocking, latches and FPGA debugging

Memory - DRAM, parity, board backends

Nexys 4 DDR - cache and panel

  • CACHE-STATUS.md - solved 31-AUG: the CPU cache, how a hit works, the four faults and their fixes, what was ruled out, test results, how to run CACHE-1X0-A00 in Verilator.
  • PLAN-cache-and-panel.md - open panel and cache items: meters not faithful, -tclargs ila dead, ruler highlight, 44155A listing question.
  • panel-clock-68705.md - the MC68705/MM58274 panel clock (TRR PANC / TRA PANS): wiring, how to enable it, how it was verified, the two DGA panel bugs.
  • HANDOFF-cga-idb-ring-cut.md - the CGA IDB combinational ring: analysis, cuts tried, what a proper fix needs (open).

MiSTer

  • PLAN-mister-storage.md - MiSTer OSD storage: open board checks, decisions, and the HPS block contract.
  • mister-microcode-loop.md - solved 01-SEP: the MiSTer WCS read took two clocks (altsyncram); now the QUARTUS_RAM_INFER arm and its equivalence gate.