ND-120 microword field layout and CPU signal names¶
This file used to be a plan for a C re-implementation of the CPU ("Architecture Implementation in C"). That port was never written and its pseudo-C was mostly guesswork, so it was cut on 28-SEP-2026 (the full old text is in git history). What is kept below is the reference part: the 64-bit microword field table, the cycle timing signal names, and the EPIC and UART command names.
For how the Verilog is laid out, read Verilog/readme.md and HARDWARE.md;
the per-module docs live next to each module in */circuit/doc/.
1. Microword fields¶
The CPU uses a 64-bit microcode instruction format with fields allocated as follows:
| Bit Range | Field Name | Description |
|---|---|---|
| 63-55 | CSALUI_8_0 | ALU Instruction (9 bits) |
| 54-53 | CSSTSS_1_0 | STS control bits (2 bits) |
| 52-51 | CSRASEL_1_0 | Register A Select (2 bits) |
| 50 | CSXREF3 | Cross Reference bit |
| 49-48 | CSRBSEL_1_0 | Register B Select (2 bits) |
| 47-46 | CSCINSEL_1_0 | Carry Input Select (2 bits) |
| 45-44 | CSALUM_1_0 | ALU Mode (2 bits) |
| 43-42 | CSMIS_1_0 | Miscellaneous bits (2 bits) |
| 41-37 | CSIDBS_4_0 | IDB Select (5 bits) |
| 36-32 | CSCOMM_4_0 | Command bits (5 bits) |
| 31-28 | CSTS_6_3 | Status bits (4 bits) |
| 27-26 | CSDELAY_1_0 | Clock cycle delay (not in CGA) |
| 25 | CSVECT | Vector control bit |
| 24 | CSSCOND | Conditional execution bit |
| 23 | CSECOND | Enable condition bit |
| 22 | CSLOOP | Loop control bit |
| 21 | CSDLY | Delay (not used in CGA) |
| 20 | CSBIT20 | Control bit 20 |
| 19-16 | CSRB_3_0 | Register B bits (4 bits) |
| 15-0 | CSBIT_15_0 | Control bits (16 bits) |
2. Cycle timing signals¶
The CPU cycle is controlled by a set of timing signals and the cycle control
bits CC0-CC3 (generated by CYC_36.v and PAL 44601B / 44307C):
- TERM - terminate signal that marks the end of a cycle.
- CC0-CC3 - cycle control bits that sequence operations within a cycle.
- MCLK - microcycle clock. One pulse per microinstruction cycle (equals TERM outside RWCS cycles); the RWCS terms in PAL_44307C stretch it so the gate array sees one long cycle while MA is used twice.
- WRFSTB - write register file strobe for updating registers.
- MACLK - micro-address latch strobe. Latch enable for the control-store address latches (CPU_CS_ACAL_17 CHIP_30H/CHIP_31F); transparent while high, captures on the falling edge. Not a memory clock.
- UCLK - microcode clock for controlling microinstruction sequences.
3. EPIC sub-commands (names only)¶
The interrupt controller is programmed through EPIC sub-commands. The numbers
and names below were in the old plan; the old plan's description of what each
one does was a guess and has been dropped. For the real behaviour read the
microprogram listing (Code/Microcode/) and DELILAH-CPU/CGA_INTR/. NOT
verified against the listing in this cleanup.
| No. (octal) | Name |
|---|---|
| 0 | MCLR |
| 1 | CLRMPID |
| 2 | MCLRMPID |
| 3 | ECLRMPID |
| 4 | LCLRMPID |
| 5 | RDVECT |
| 6 | RDSTAT |
| 7 | RDMPIE |
| 10 | LDMPIE (inhibit all) |
| 11 | LDSTAT |
| 12 | MCLRMPIE |
| 13 | MSETMPIE |
| 14 | CLRMPIE |
| 15 | DISINTRQ |
| 16 | LDMPIE (load mask) |
| 17 | ENINTRQ |
4. UART commands (COMM 5)¶
The UART is reached through COMM 5, with the MIS field (bits 1:0) selecting the register:
| COMM (octal) | MIS (octal) | Command | Description |
|---|---|---|---|
| 5 | 0 | UART DATA | Read/write UART data register |
| 5 | 1 | UART STAT | Read/write UART status register |
| 5 | 2 | UART MODE | Set UART mode register |
| 5 | 3 | UART COMM | Configure UART command register |