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Verilog modules

Every module of the design has its own page: what it is, a table of its ports, and a picture of its symbol. Each page is made from the //! comments in the module's source. 394 modules in 16 areas.

What sits inside what, for the simulation and for every FPGA board, is on HIERARCHY.md (made from a yosys elaboration).

Top level (the whole machine)

Module What it is Source
ND120_CORE ND3202D CPU board + the optional ND-BUS Verilog device chain. ND120_CORE.v
ND120_TOP - ND120_TOP.v

DELILAH CPU gate array (CGA)

Module What it is Source
BusDriver16 BusDriver16 DELILAH-CPU/CGA/circuit/BusDriver16.v
CGA CGA TOP LEVEL DELILAH-CPU/CGA/circuit/CGA.v
CGA_ALU OUT MUX DELILAH-CPU/CGA_ALU/circuit/CGA_ALU.v
CGA_ALU_ARG ARG REGISTER DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_ARG.v
CGA_ALU_DBR DBR REGISTER (Data Bus Register) DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_DBR.v
CGA_ALU_GPR CGA/ALU/GPR DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_GPR.v
CGA_ALU_OUTMUX OUT MUX DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_OUTMUX.v
CGA_ALU_OUTMUX_IDBS IDBS MUX DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_OUTMUX_IDBS.v
CGA_ALU_OUTMUX_SEL8 SEL8 DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_OUTMUX_SEL8.v
CGA_ALU_QREG Q REGISTER DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_QREG.v
CGA_ALU_RALU_LOGOP LOGOP DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_RALU_LOGOP.v
CGA_ALU_RALU_MUX216L LOGOP DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_RALU_MUX216L.v
CGA_ALU_SHIFT CGA/ALU/SHIFT DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_SHIFT.v
CGA_ALU_SMUX SMUX DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_SMUX.v
CGA_ALU_STS STS REGISTER DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_STS.v
CGA_ALU_SWAP SWAP REGISTER DELILAH-CPU/CGA_ALU/circuit/CGA_ALU_SWAP.v
CGA_CPU_ALU_CONTR ALU CONTROLLER DELILAH-CPU/CGA_ALU/circuit/CGA_CPU_ALU_CONTR.v
CGA_CPU_ALU_OUTMUX_SEL7 SEL7 DELILAH-CPU/CGA_ALU/circuit/CGA_CPU_ALU_OUTMUX_SEL7.v
CGA_CPU_ALU_RALU RALU DELILAH-CPU/CGA_ALU/circuit/CGA_CPU_ALU_RALU.v
CGA_CPU_ALU_RMUX REGISTER MUX DELILAH-CPU/CGA_ALU/circuit/CGA_CPU_ALU_RMUX.v
CGA_DCD CPU GATE ARRAY - CGA - DELILAH DELILAH-CPU/CGA_DCD/circuit/CGA_DCD.v
CGA_IDBCTL CPU GATE ARRAY - CGA - DELILAH DELILAH-CPU/CGA_IDBCTL/circuit/CGA_IDBCTL.v
CGA_IDBCTL_PGSREG CPU GATE ARRAY - CGA - DELILAH DELILAH-CPU/CGA_IDBCTL/circuit/CGA_IDBCTL_PGSREG.v
CGA_IDBCTL_SEL6 CPU GATE ARRAY - CGA - DELILAH DELILAH-CPU/CGA_IDBCTL/circuit/CGA_IDBCTL_SEL6.v
CGA_INTR CPU GATE ARRAY - CGA - DELILAH DELILAH-CPU/CGA_INTR/circuit/CGA_INTR.v
CGA_INTR_CNTLR INTERRUPT CONTROLLER DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR.v
CGA_INTR_CNTLR_CLR CLR DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_CLR.v
CGA_INTR_CNTLR_CLR_CLRBIT CLRBIT DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_CLR_CLRBIT.v
CGA_INTR_CNTLR_IRGEL IRGEL DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL.v
CGA_INTR_CNTLR_IRGEL_HIGEL HIGEL DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_HIGEL.v
CGA_INTR_CNTLR_IRGEL_HIRL HIRL DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_HIRL.v
CGA_INTR_CNTLR_IRGEL_LOGEL LOGEL DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_LOGEL.v
CGA_INTR_CNTLR_IRGEL_LORL LO RL DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_LORL.v
CGA_INTR_CNTLR_IRGEL_VMUX VECTOR MUX DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRGEL_VMUX.v
CGA_INTR_CNTLR_IRQ IRQ DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ.v
CGA_INTR_CNTLR_IRQ_MASK IRQ MASK DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_MASK.v
CGA_INTR_CNTLR_IRQ_MASK_MASKBIT IRQ MASK BIT DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_MASK_MASKBIT.v
CGA_INTR_CNTLR_IRQ_MREQ MREQ DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_MREQ.v
CGA_INTR_CNTLR_IRQ_REG INTERRUPT CONTROLLER REGISTER DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_REG.v
CGA_INTR_CNTLR_IRQ_REG_RQBIT INTERRUPT CONTROLLER REGISTER Q BIT DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_REG_RQBIT.v
CGA_INTR_CNTLR_IRQ_REG_RQBIT_V2 INTERRUPT CONTROLLER REGISTER Q BIT - loop-free replacement DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_IRQ_REG_RQBIT_V2.v
CGA_INTR_CNTLR_MDCD MDCD DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_MDCD.v
CGA_INTR_CNTLR_VECGEN Vector Generator DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN.v
CGA_INTR_CNTLR_VECGEN_CMP CMP DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_CMP.v
CGA_INTR_CNTLR_VECGEN_CMP_MAGCMP MAGCMP DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_CMP_MAGCMP.v
CGA_INTR_CNTLR_VECGEN_ISMUX ISMUX DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_ISMUX.v
CGA_INTR_CNTLR_VECGEN_OSMUX osmux DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_OSMUX.v
CGA_INTR_CNTLR_VECGEN_PTY VECTOR GENERATOR DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_PTY.v
CGA_INTR_CNTLR_VECGEN_PTY_PTYENC PRIORITY ENCODER DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_PTY_PTYENC.v
CGA_INTR_CNTLR_VECGEN_STAT STAT DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_STAT.v
CGA_INTR_CNTLR_VECGEN_STAT_SBIT S BIT DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_STAT_SBIT.v
CGA_INTR_CNTLR_VECGEN_VHR VHR DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_CNTLR_VECGEN_VHR.v
CGA_INTR_IRSRC Interrupt Source DELILAH-CPU/CGA_INTR/circuit/CGA_INTR_IRSRC.v
CGA_MAC MAC DELILAH-CPU/CGA_MAC/circuit/CGA_MAC.v
CGA_MAC_ADD ADD DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_ADD.v
CGA_MAC_AP09 AP09 DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_AP09.v
CGA_MAC_APOS_CALCA CALCA DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_APOS_CALCA.v
CGA_MAC_APOS_INC INCREMENT DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_APOS_INC.v
CGA_MAC_DECODE INCREMENT DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_DECODE.v
CGA_MAC_FASTADD ADD DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_FASTADD.v
CGA_MAC_LA1025 ADD DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_LA1025.v
CGA_MAC_LASEL LASEL DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_LASEL.v
CGA_MAC_PTSEL PTSEL DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_PTSEL.v
CGA_MAC_SEGPT SEGPT DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_SEGPT.v
CGA_MAC_SEGPT_PCR PCR REGISTER DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_SEGPT_PCR.v
CGA_MAC_SEGPT_SEG SEGMENT REGISTER DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_SEGPT_SEG.v
CGA_MAC_SEGPT_XPT XPT DELILAH-CPU/CGA_MAC/circuit/CGA_MAC_SEGPT_XPT.v
CGA_MIC MIC DELILAH-CPU/CGA_MIC/circuit/CGA_MIC.v
CGA_MIC_CONDREG CONDITION REGISTER DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_CONDREG.v
CGA_MIC_CSEL CONDITION SELECT DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_CSEL.v
CGA_MIC_IINC INSTRUCTION INCREMENT DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_IINC.v
CGA_MIC_INCOUNT INCOUNT DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_INCOUNT.v
CGA_MIC_IPOS INSTRUCTION POSITION DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_IPOS.v
CGA_MIC_MASEL Microcode Address SELECT DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_MASEL.v
CGA_MIC_MASEL_REPEAT REPEAT DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_MASEL_REPEAT.v
CGA_MIC_STACK Microcode STACK DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_STACK.v
CGA_MIC_STACK_BIT BIT DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_STACK_BIT.v
CGA_MIC_STACK_BIT12 BIT12 DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_STACK_BIT12.v
CGA_MIC_WCAREG WCAREG DELILAH-CPU/CGA_MIC/circuit/CGA_MIC_WCAREG.v
CGA_TESTMUX TESTMUX DELILAH-CPU/CGA_TESTMUX/circuit/CGA_TESTMUX.v
CGA_TRAP Trap DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP.v
CGA_TRAP_BRKDET BREAK DETECTION (?) DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP_BRKDET.v
CGA_TRAP_TBUF TRAP BUFFERS DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP_TBUF.v
CGA_TRAP_TVGEN Trap Vector Generator (?) DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP_TVGEN.v
CGA_TRAP_TVGEN_P2 P2 DELILAH-CPU/CGA_TRAP/circuit/CGA_TRAP_TVGEN_P2.v
CGA_WRF WRF: Working Register File DELILAH-CPU/CGA_WRF/circuit/CGA_WRF.v
CGA_WRF_RBLOCK WRF: Working Register File DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK.v
CGA_WRF_RBLOCK_DR16 WRF: Working Register File DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_DR16.v
CGA_WRF_RBLOCK_LR16 WRF: Working Register File DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_LR16.v
CGA_WRF_RBLOCK_PREG WRF: Working Register File DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_PREG.v
CGA_WRF_RBLOCK_SEL16 WRF: Working Register File DELILAH-CPU/CGA_WRF/circuit/CGA_WRF_RBLOCK_SEL16.v
ND120_PF_CAPTURE WHAT THIS IS FOR DELILAH-CPU/CGA/circuit/ND120_PF_CAPTURE.v

Decoder gate array (DGA)

Module What it is Source
DECODE_DGA PDF Page 2 -> DECODE - DECODE_DGA- Sheet 1 of 6 DECODE-GateArray/DGA/circuit/DECODE_DGA.v
DECODE_DGA_COMM DGA (Decode Gate Array) DECODE-GateArray/DGA/circuit/DECODE_DGA_COMM.v
DECODE_DGA_IDBS Decode Internal Databus SOURCE (IDBS). Generates ENABLE signals for DECODE-GateArray/DGA/circuit/DECODE_DGA_IDBS.v
DECODE_DGA_POW DECODE/DGA/POW DECODE-GateArray/DGA/circuit/DECODE_DGA_POW.v
F091 NEC F091 - H,L LEVEL GENERATOR DECODE-GateArray/DGA/circuit/F091.v
F103 NEC F103 - Inverter x3 signal drive DECODE-GateArray/DGA/circuit/F103.v
F571 NEC F571 - 2 TO 1 MULTIPLEXER DECODE-GateArray/DGA/circuit/F571.v
F595 NEC F595 - R/S Latch with Gated input DECODE-GateArray/DGA/circuit/F595.v
F617 NEC F617 - D Flip-Flop with RB, SB DECODE-GateArray/DGA/circuit/F617.v
F714 NEC F714 - T Flip-Flop with R, S DECODE-GateArray/DGA/circuit/F714.v
F924 NEC F924 - 4-BIT D-TYPE FLIP-FLOP DECODE-GateArray/DGA/circuit/F924.v

CPU board 3202D

Module What it is Source
BIF_5 BUS INTERFACE CPU-BOARD-3202/circuit/BIF_5.v
BIF_BCTL_6 BIF CONTROL CPU-BOARD-3202/circuit/BIF_BCTL_6.v
BIF_BCTL_BDRV_7 BUS DRIVER CPU-BOARD-3202/circuit/BIF_BCTL_BDRV_7.v
BIF_BCTL_SYNC_8 BIF SYNC CPU-BOARD-3202/circuit/BIF_BCTL_SYNC_8.v
BIF_DPATH_9 BIF DATA PATH CPU-BOARD-3202/circuit/BIF_DPATH_9.v
BIF_DPATH_BDLBD_10 BIF BD TO LBD CPU-BOARD-3202/circuit/BIF_DPATH_BDLBD_10.v
BIF_DPATH_CDLBD_11 BIF CD TO LBD CPU-BOARD-3202/circuit/BIF_DPATH_CDLBD_11.v
BIF_DPATH_LDBCTL_12 IO DECODING CPU-BOARD-3202/circuit/BIF_DPATH_LDBCTL_12.v
BIF_DPATH_PESPEA_13 BIF PES & PEA CPU-BOARD-3202/circuit/BIF_DPATH_PESPEA_13.v
BIF_DPATH_PPNLBD_14 BIF PPN TO LBD CPU-BOARD-3202/circuit/BIF_DPATH_PPNLBD_14.v
CPU_15 CPU CPU-BOARD-3202/circuit/CPU_15.v
CPU_CS_16 CONTROL STORE CPU-BOARD-3202/circuit/CPU_CS_16.v
CPU_CS_ACAL_17 MICRO ADDR CALC UNIT CPU-BOARD-3202/circuit/CPU_CS_ACAL_17.v
CPU_CS_CTL_18 CS CONTROL CPU-BOARD-3202/circuit/CPU_CS_CTL_18.v
CPU_CS_PROM_19 PROMS CPU-BOARD-3202/circuit/CPU_CS_PROM_19.v
CPU_CS_PROM_19_ORG Logisim-evolution goes FPGA automatic generated Verilog code CPU-BOARD-3202/circuit/CPU_CS_PROM_19_ORG.v
CPU_CS_TCV_20 CS TRANSCEIVERS CPU-BOARD-3202/circuit/CPU_CS_TCV_20.v
CPU_CS_WCS_21_22 Writable Control Store CPU-BOARD-3202/circuit/CPU_CS_WCS_21_22.v
CPU_MMU_24 MMU TOP LEVEL CPU-BOARD-3202/circuit/CPU_MMU_24.v
CPU_MMU_CACHE_25 CACHE CPU-BOARD-3202/circuit/CPU_MMU_CACHE_25.v
CPU_MMU_CSR_26 CACHE STATUS REGISER CPU-BOARD-3202/circuit/CPU_MMU_CSR_26.v
CPU_MMU_HIT_27 HIT DETECTOR CPU-BOARD-3202/circuit/CPU_MMU_HIT_27.v
CPU_MMU_PPNX_28 PPN TO IDB CPU-BOARD-3202/circuit/CPU_MMU_PPNX_28.v
CPU_MMU_PT_29 CACHE CPU-BOARD-3202/circuit/CPU_MMU_PT_29.v
CPU_MMU_PTIDB_30 PT TO IDB CPU-BOARD-3202/circuit/CPU_MMU_PTIDB_30.v
CPU_MMU_WCA_31 PPN TO CPN CPU-BOARD-3202/circuit/CPU_MMU_WCA_31.v
CPU_PROC_32 PROCESSOR TOP LEVEL CPU-BOARD-3202/circuit/CPU_PROC_32.v
CPU_PROC_CGA_33 CPU GATE ARRAY CPU-BOARD-3202/circuit/CPU_PROC_CGA_33.v
CPU_PROC_CMDDEC_34 COMMAND & IDB DECODE CPU-BOARD-3202/circuit/CPU_PROC_CMDDEC_34.v
CPU_STOC_35 IDB TO CD CPU-BOARD-3202/circuit/CPU_STOC_35.v
CYC_36 CYC CPU-BOARD-3202/circuit/CYC_36.v
CYC_CC_D CYC_CC_D CPU-BOARD-3202/circuit/CYC_CC_D.v
CYC_TERM_D CYC_TERM_D CPU-BOARD-3202/circuit/CYC_TERM_D.v
IO_37 IO CPU-BOARD-3202/circuit/IO_37.v
IO_DCD_38 IO DECODING CPU-BOARD-3202/circuit/IO_DCD_38.v
IO_PANCAL_40 PANEL PROC & CALENDAR CPU-BOARD-3202/circuit/IO_PANCAL_40.v
IO_REG_41 IOC, ALD & INR REGS CPU-BOARD-3202/circuit/IO_REG_41.v
IO_UART_42 UART & IOR REG CPU-BOARD-3202/circuit/IO_UART_42.v
MEM_43 MEM CPU-BOARD-3202/circuit/MEM_43.v
MEM_ADDR_44 MEM ADDR MUX CPU-BOARD-3202/circuit/MEM_ADDR_44.v
MEM_ADEC_45 ADDRESS DECODERS CPU-BOARD-3202/circuit/MEM_ADEC_45.v
MEM_DATA_46 DATA & PARITY TCV CPU-BOARD-3202/circuit/MEM_DATA_46.v
MEM_ERROR_47 LOCAL PES & PEA CPU-BOARD-3202/circuit/MEM_ERROR_47.v
MEM_LBDIF_48 LOCAL BD CONTROL CPU-BOARD-3202/circuit/MEM_LBDIF_48.v
MEM_RAM_49 LOCAL RAM CPU-BOARD-3202/circuit/MEM_RAM_49.v
MEM_RAM_49_BLOCKRAM MEM/RAM - block-RAM backend (any FPGA) CPU-BOARD-3202/circuit/MEM_RAM_49_BLOCKRAM.v
MEM_RAM_49_SIM MEM/RAM - Verilator simulation backend CPU-BOARD-3202/circuit/MEM_RAM_49_SIM.v
MEM_RAMC_50 LOCAL RAM CONTROL CPU-BOARD-3202/circuit/MEM_RAMC_50.v
ND3202D CPU CPU-BOARD-3202/circuit/ND3202D.v
PAL_44445B_D PAL_44445B_D - sysclk-domain mirror of PAL_44445B (UCADEC) CPU-BOARD-3202/circuit/PAL_44445B_D.v
PAL_44446B_D PAL_44446B_D - sysclk-domain mirror of PAL_44446B (UBADEC) CPU-BOARD-3202/circuit/PAL_44446B_D.v
PANCAL_68705_CLOCK PANCAL_68705_CLOCK CPU-BOARD-3202/circuit/PANCAL_68705_CLOCK.v

PAL chips

Module What it is Source
PAL_16L8 - PAL/template/PAL18L8.v
PAL_16R4 - PAL/template/PAL16R4.v
PAL_44302B Component PAL 44302B PAL/PAL_44302B.v
PAL_44303B Component PAL 44303B PAL/PAL_44303B.v
PAL_44304E Component PAL 44304E PAL/PAL_44304E.v
PAL_44305D Component PAL 44305D PAL/PAL_44305D.v
PAL_44306A Component PAL 44306A PAL/PAL_44306A.v
PAL_44307C Component PAL 44307C PAL/PAL_44307C.v
PAL_44310D Component PAL 44310D PAL/PAL_44310D.v
PAL_44401B Component PAL 44401B PAL/PAL_44401B.v
PAL_44402D Component PAL 44402D PAL/PAL_44402D.v
PAL_44402D_EN Component PAL 44402D - clock-enable variant PAL/PAL_44402D_EN.v
PAL_44403C Component PAL 44403C PAL/PAL_44403C.v
PAL_44403C_EN Component PAL 44403C - clock-enable wrapper PAL/PAL_44403C_EN.v
PAL_44404C Component PAL 44404C PAL/PAL_44404C.v
PAL_44404C_EN Component PAL 44404C - clock-enable wrapper PAL/PAL_44404C_EN.v
PAL_44407A Component PAL 44407A PAL/PAL_44407A.v
PAL_44407A_EN Component PAL 44407A (UERFIX) - clock-enable wrapper PAL/PAL_44407A_EN.v
PAL_44408B Component PAL 44608A PAL/PAL_44408B.v
PAL_44408B_EN Component PAL 44408B (VEXFIX) - clock-enable wrapper PAL/PAL_44408B_EN.v
PAL_44445B Component PAL 44445B PAL/PAL_44445B.v
PAL_44446B Component PAL 44446B PAL/PAL_44446B.v
PAL_44511A Component PAL 44511A PAL/PAL_44511A.v
PAL_44511A_EN Component PAL 44511A (LEV0) - clock-enable wrapper PAL/PAL_44511A_EN.v
PAL_44601B Component PAL 44601B PAL/PAL_44601B.v
PAL_44801A Component PAL 44801A PAL/PAL_44801A.v
PAL_44803A Component PAL 44803A PAL/PAL_44803A.v
PAL_44902A Component PAL 44902A PAL/PAL_44902A.v
PAL_44904B Component PAL 44904B PAL/PAL_44904B.v
PAL_45001B Component PAL 45001B PAL/PAL_45001B.v
PAL_45008B Component PAL 45008B PAL/PAL_45008B.v
PAL_45009B Component PAL 45009B PAL/PAL_45009B.v

Shared chips and support logic

Module What it is Source
A02 CGA A02 component Shared/ndlib/A02.v
Adder Component : Adder Shared/logisim/Adder.v
AM29833A Module AM29833A Shared/support/AM29833A.v
AM29841 Component AM29841 Shared/support/AM29841.v
AM29861A AM29861A Shared/support/AM29861A.v
AM29C821 AM29C821 Shared/support/AM29C821.v
Am9150 Component Am9150 Shared/support/Am9150.v
Am9150_w_clock Am9150 1024x4 High-Speed Static R/W RAM Shared/support/Am9150_with_clk.v
AND_GATE Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/AND_GATE.v
AND_GATE_3_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/AND_GATE_3_INPUTS.v
AND_GATE_4_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/AND_GATE_4_INPUTS.v
AND_GATE_5_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/AND_GATE_5_INPUTS.v
AND_GATE_6_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/AND_GATE_6_INPUTS.v
BACKWIRING_PROM BACK-WIRING PROM (installation number PROM) Shared/support/BACKWIRING_PROM.v
BD4TU Component : BD4TU Shared/ndlib/BD4TU.v
CMP4 Component: CMP4 (4 bit comparator) Shared/ndlib/CMP4.v
Comparator Component: Comparator Shared/logisim/Comparator.v
D_FLIPFLOP D FLIP-FLOP Shared/logisim/D_FLIPFLOP.v
D_FLIPFLOP_EN D_FLIPFLOP_EN - D_FLIPFLOP with an optional clock-enable mode. Shared/ndlib/D_FLIPFLOP_EN.v
D_FLIPFLOP_SIMPLE D FLIP-FLOP (Wihtout SET or RESET) Shared/logisim/D_FLIPFLOP_SIMPLE.v
Decoder_4 Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/Decoder_4.v
Decoder_8 Component : Decoder_8 Shared/logisim/Decoder_8.v
F924_EN F924_EN - F924 (NEC 4-bit D-type flip-flop) with an optional Shared/ndlib/F924_EN.v
FIFO_8BIT FIFO 8 bit Shared/support/FIFO_8BIT.v
FullAdder Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/FullAdder.v
IDT6168A_20 IDT6168A Shared/support/IDT6168A_20.v
IMS1403_25 Component : IMS1403_25 Shared/support/IMS1403_25.v
J_K_FLIPFLOP J-K FLIP-FLOP Shared/logisim/J_K_FLIPFLOP.v
J_K_FLIPFLOP_EN J_K_FLIPFLOP_EN - J_K_FLIPFLOP with an optional clock-enable mode. Shared/ndlib/J_K_FLIPFLOP_EN.v
L4 Component L4 (4-bit latch) Shared/ndlib/L4.v
L8 Component L8 (8-bit latch) Shared/ndlib/L8.v
LATCH Component LATCH Shared/ndlib/LATCH.v
M169C M169C - 74LS169 - Synchronous 4-bit up/down binary counters Shared/ndlib/M169C.v
M169C_EN M169C_EN - M169C (74LS169 synchronous 4-bit up/down binary counter) Shared/ndlib/M169C_EN.v
Multiplexer_2 Component : Multiplexer_2 Shared/logisim/Multiplexer_2.v
Multiplexer_2_w_enable Component : Multiplexer_2_w_enable Shared/logisim/Multiplexer_2_w_enable.v
Multiplexer_4 Component : Multiplexer_4 Shared/logisim/Multiplexer_4.v
Multiplexer_8 Component : Multiplexer_8 Shared/logisim/Multiplexer_8.v
Multiplexer_bus_2 Component : Multiplexer_bus_2 Shared/logisim/Multiplexer_bus_2.v
MUX21L Component : MUX21L Shared/ndlib/MUX21L.v
MUX21LP Component : MUX21LP (2-to-1 Multiplexer NEGATED) Shared/ndlib/MUX21LP.v
MUX24P - Shared/ndlib/MUX24P.v
MUX31LP Component : MUX31LP Shared/ndlib/MUX31LP.v
MUX34P Component: MUX34P Shared/ndlib/MUX34P.v
MUX41P Component : MUX41P Shared/ndlib/MUX41P.v
MUX81 Component: MUX81 Shared/ndlib/MUX81.v
NAND_GATE Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NAND_GATE.v
NAND_GATE_3_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NAND_GATE_3_INPUTS.v
NAND_GATE_4_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NAND_GATE_4_INPUTS.v
NAND_GATE_5_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NAND_GATE_5_INPUTS.v
NAND_GATE_6_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NAND_GATE_6_INPUTS.v
NAND_GATE_7_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NAND_GATE_7_INPUTS.v
NAND_GATE_8_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NAND_GATE_8_INPUTS.v
ND120_LATCH Component LATCH Shared/ndlib/LATCH.v
ND38GHP Component : ND38GHP (3-to-8 decoder) Shared/ndlib/ND38GHP.v
ND38GLP Component : ND38GLP (3-to-8 decoder) Shared/ndlib/ND38GLP.v
NOR_GATE Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NOR_GATE.v
NOR_GATE_3_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NOR_GATE_3_INPUTS.v
NOR_GATE_4_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/NOR_GATE_4_INPUTS.v
OR_GATE Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/OR_GATE.v
OR_GATE_3_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/OR_GATE_3_INPUTS.v
OR_GATE_4_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/OR_GATE_4_INPUTS.v
OR_GATE_5_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/OR_GATE_5_INPUTS.v
OR_GATE_6_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/OR_GATE_6_INPUTS.v
OR_GATE_7_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/OR_GATE_7_INPUTS.v
OR_GATE_8_INPUTS Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/OR_GATE_8_INPUTS.v
R41P Component : R41P Shared/ndlib/R41P.v
R41P_EN R41P_EN - R41P (4-bit register, true+complement outputs) with an Shared/ndlib/R41P_EN.v
R81 Component : R81 (8-bit register. Latched on RISING EDGE) Shared/ndlib/R81.v
R81_EN R81_EN - R81 (8-bit register, true+complement outputs) with an Shared/ndlib/R81_EN.v
R81P Component : R81P (8 bit flip flop with Q and QN outputs. Latched on rising edge) Shared/ndlib/R81P.v
RMUX_Gates Component : RMUX_Gates Shared/ndlib/RMUX_Gates.v
SC2661_UART SC2661 UART Shared/support/SC2661_UART.v
SCAN_FF SCAN FLIP-FLOP (Also known as FDIS in the DELILAH schematics) Shared/ndlib/SCAN_FF.v
SCAN_FF_EN SCAN_FF_EN - SCAN_FF with an optional clock-enable mode. Shared/ndlib/SCAN_FF_EN.v
SCAN_WITH_RESET_N Component : SCAN_WITH_RESET_N Shared/ndlib/SCAN_WITH_RESET_N.v
SCAN_WITH_RESET_N_EN SCAN_WITH_RESET_N_EN - SCAN_WITH_RESET_N with an optional Shared/ndlib/SCAN_WITH_RESET_N_EN.v
SCAN_WITH_SET_N SCAN WITH SET FLIP-FLOP Shared/ndlib/SCAN_WITH_SET_N.v
SCAN_WITH_SET_N_EN SCAN_WITH_SET_N_EN - SCAN_WITH_SET_N with an optional clock-enable Shared/ndlib/SCAN_WITH_SET_N_EN.v
SevenSegDebug 7-Segment Display Debug Module for Basys3 Shared/support/SevenSegDebug.v
SIP1M9 RAM CHIP 1 MBYTE (1024KB) Shared/support/SIP1M9.v
SR44 Component SR44 Shared/ndlib/SR44.v
SR44_EN SR44_EN - SR44 (4-bit load/shift register) with an optional Shared/ndlib/SR44_EN.v
T_FLIPFLOP Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/T_FLIPFLOP.v
TMM2018D_25 TMM2018D_25 | 16K bit Static RAM (Used by Cache and Page Tables) Shared/support/TMM2018D_25.v
TTL_74139 TTL 74139 Shared/support/TTL_74139.v
TTL_74241 Component : TTL_74241 Shared/support/TTL_74241.v
TTL_74244 - Shared/support/TTL_74244.v
TTL_74245 Component : TTL_74245 Shared/support/TTL_74245.v
TTL_74273 74273 Shared/support/TTL_74273.v
TTL_74373 Module 74PCT373 Shared/support/TTL_74373.v
TTL_74374 Component : 74LS374 Shared/support/TTL_74374.v
TTL_74393 - Shared/support/TTL_74393.v
TTL_74521 Component: MUX81 Shared/support/TTL_74521.v
TTL_74534 Component : TTL_74534 Shared/support/TTL_74534.v
TTL_74646 Component : TTL_74646 Shared/support/TTL_74646.v
TTL_74648 Component : TTL_74648 Shared/support/TTL_74648.v
XNOR_GATE_ONEHOT Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/XNOR_GATE_ONEHOT.v
XOR_GATE_ONEHOT Logisim-evolution goes FPGA automatic generated Verilog code Shared/logisim/XOR_GATE_ONEHOT.v

ND-bus devices (floppy, Winchester, tape)

Module What it is Source
ND_BUS_SLAVE ND-100 BUS SLAVE ADAPTER ND-BUS-DEVICES/BUS-IF/circuit/ND_BUS_SLAVE.v
ND_DMA_MASTER ND-100 DMA BUS MASTER ND-BUS-DEVICES/DMA/circuit/ND_DMA_MASTER.v
ND_FLOPPY_DMA - ND-BUS-DEVICES/FLOPPY-DMA/circuit/ND_FLOPPY_DMA.v
ND_FLOPPY_PIO ND-100 FLOPPY DISK CONTROLLER, PIO INTERFACE (3027 style) ND-BUS-DEVICES/FLOPPY/circuit/ND_FLOPPY_PIO.v
ND_SMD - ND-BUS-DEVICES/SMD/circuit/ND_SMD.v
ND_TAPE_400 ND-100 PAPERTAPE READER, DEVICE 400 (octal) ND-BUS-DEVICES/TAPE-400/circuit/ND_TAPE_400.v
ND_WINCHESTER - ND-BUS-DEVICES/WINCHESTER/circuit/ND_WINCHESTER.v

SD card and FAT file system

Module What it is Source
nd_storage nd_storage - multi-client storage facade (top level) SD-FAT/circuit/nd_storage.v
nd_storage_cache nd_storage_cache - tag / LRU directory for the shared block cache SD-FAT/circuit/nd_storage_cache.v
nd_storage_devices nd_storage_devices - board-agnostic BOOT.BPUN byte source for the SD-FAT/circuit/nd_storage_devices.v
nd_storage_disc_adapter - SD-FAT/circuit/nd_storage_disc_adapter.v
nd_storage_engine - SD-FAT/circuit/nd_storage_engine.v
nd_storage_fatchk nd_storage mount-time contiguity checker (fatchk) SD-FAT/circuit/nd_storage_fatchk.v
nd_storage_floppy_adapter - SD-FAT/circuit/nd_storage_floppy_adapter.v
nd_storage_mount nd_storage open/preload FSM (mount) SD-FAT/circuit/nd_storage_mount.v
nd_storage_tape_adapter nd_storage_tape_adapter - byte-stream adapter for the paper-tape reader SD-FAT/circuit/nd_storage_tape_adapter.v
nds_sync_level nd_storage CDC synchronizer primitives SD-FAT/circuit/nds_sync.v
nds_sync_pulse nd_storage CDC synchronizer primitives SD-FAT/circuit/nds_sync.v
sd_card_ctrl SD card init + FAT16/FAT32 mount + root-directory scan + file stream SD-FAT/circuit/sd_file_reader.v
sd_fat_check FAT cluster-chain validator ("fsck-lite") SD-FAT/circuit/sd_fat_check.v
sd_fat_freescan FAT free-space scanner SD-FAT/circuit/sd_fat_freescan.v
sd_fat_rewrite FAT16/FAT32 in-place file replacement ("delete + recreate") SD-FAT/circuit/sd_fat_rewrite.v
sd_file_reader SD card init + FAT16/FAT32 mount + root-directory scan + file stream SD-FAT/circuit/sd_file_reader.v
sd_writer SD sector read/write engine (single + multi-block, SD-native 1-bit) SD-FAT/circuit/sd_writer.v

Terminals (TDV2200 screen and keyboard)

Module What it is Source
byte_fifo - Terminals/rtl/byte_fifo.v
cdc_byte - Terminals/rtl/cdc_byte.v
char_ram - Terminals/rtl/char_ram.v
console_uart_rx - Terminals/rtl/console_uart_rx.v
console_uart_tx - Terminals/rtl/console_uart_tx.v
font_rom - Terminals/rtl/font_rom.v
key_tdv2200 - Terminals/rtl/key_tdv2200.v
key_vt100 - Terminals/rtl/key_vt100.v
mips_counter - Terminals/rtl/mips_counter.v
ps2_ascii_table - Terminals/rtl/ps2_ascii_table.v
ps2_ascii_table_tdv - Terminals/rtl/ps2_ascii_table_tdv.v
ps2_decoder - Terminals/rtl/ps2_decoder.v
ps2_decoder_tdv - Terminals/rtl/ps2_decoder_tdv.v
ps2_keyboard - Terminals/rtl/ps2_keyboard.v
ps2_keyboard_tdv - Terminals/rtl/ps2_keyboard_tdv.v
rate_meter - Terminals/rtl/rate_meter.v
ratio_meter - Terminals/rtl/ratio_meter.v
term_banner - Terminals/rtl/term_banner.v
term_banner_rom - Terminals/rtl/term_banner_rom.v
term_console_feed - Terminals/rtl/term_console_feed.v
term_panel - Terminals/rtl/term_panel.v
term_panel_rom - Terminals/rtl/term_panel_rom.v
terminal_ctrl - Terminals/rtl/terminal_ctrl.v
terminal_ctrl_tdv - Terminals/rtl/terminal_ctrl_tdv.v
terminal_top - Terminals/rtl/terminal_top.v
text_screen - Terminals/rtl/text_screen.v
vga_timing - Terminals/rtl/vga_timing.v

FPGA board: basys3

Module What it is Source
basys3_mem_test_top Basys3 standalone memory test for the ND-120 BRAM path fpga/basys3/mem-test/basys3_mem_test_top.v
basys3_sd_fat_top Basys3 wrapper for the SD-FAT test (sd_fat_test_top) fpga/basys3/sd-fat-test/basys3_sd_fat_top.v
msg_printer UART message printer for the SDRAM test fpga/basys3/mem-test/msg_printer.v
uart_tx UART transmitter (8N1) fpga/basys3/mem-test/uart_tx.v

FPGA board: cmod-a7-35t

Module What it is Source
nd120_cmod_top Cmod A7-35T wrapper for the ND-120 CPU (ND120_TOP, BRAM main memory) fpga/cmod-a7-35t/nd120_cmod_top.v

FPGA board: mega65

Module What it is Source
m65_keys_to_ps2 - fpga/mega65/rtl/m65_keys_to_ps2.v
nd120_console_mega65 - fpga/mega65/rtl/nd120_console_mega65.v
nd120_mega65_machine - fpga/mega65/rtl/nd120_mega65_machine.v
nd_avalon_port nd_avalon_port - the nd_ddr2_port contract on an Avalon-MM 16-bit master fpga/mega65/rtl/nd_avalon_port.v
nd_storage_mega65_devices - fpga/mega65/rtl/nd_storage_mega65_devices.v
nd_storage_vdrives - fpga/mega65/rtl/nd_storage_vdrives.v

FPGA board: mister

Module What it is Source
emu - fpga/mister/nd120.sv
nd120_console_mister - fpga/mister/rtl/nd120_console_mister.v
nd120_csa_trace nd120_csa_trace.v - print the last N microcode addresses, in order fpga/mister/rtl/nd120_csa_trace.v
nd120_diag_print nd120_diag_print.v - CPU state, printed onto the console fpga/mister/rtl/nd120_diag_print.v
nd120_sterr_catch nd120_sterr_catch.v - catch the self-test failure and report its number fpga/mister/rtl/nd120_sterr_catch.v
nd120_storage_probe nd120_storage_probe.v - storage mount + Winchester activity, on the fpga/mister/rtl/nd120_storage_probe.v
nd_storage_hps - fpga/mister/rtl/nd_storage_hps.v
nd_storage_mister_devices - fpga/mister/rtl/nd_storage_mister_devices.v
pll_cpu - fpga/mister/rtl/pll_cpu.v

FPGA board: nexys4ddr

Module What it is Source
board_test_top Nexys 4 DDR board check - proves the parts the ND-120 build depends on fpga/nexys4ddr/board-test/board_test_top.v
floppy_hwtest_core floppy_hwtest_core - the self-checking floppy DMA hardware test proper: fpga/nexys4ddr/floppy-hw-test/floppy_hwtest_core.v
floppy_hwtest_top floppy_hwtest_top - SELF-CHECKING VERILOG TEST PROGRAM ON THE REAL fpga/nexys4ddr/floppy-hw-test/floppy_hwtest_top.v
floppy_seam_top floppy_seam_top - autonomous silicon probe for the Nexys 4 DDR floppy fpga/nexys4ddr/floppy-seam-test/floppy_seam_top.v
MEM_RAM_49_DDR2 MEM/RAM - DDR2 backend (Nexys 4 DDR) fpga/nexys4ddr/ddr2/MEM_RAM_49_DDR2.v
nd120_errfa_wdiox_ring Captures the last 48 IOX accesses to the Winchester card (IOX fpga/nexys4ddr/nd120_errfa_wdiox_ring.v
nd120_nexys4ddr_top Nexys 4 DDR / Nexys A7-100T top level for the ND-120 fpga/nexys4ddr/nd120_nexys4ddr_top.v
nd_ddr2_arb nd_ddr2_arb - two clients on one nd_ddr2_port fpga/nexys4ddr/ddr2/nd_ddr2_arb.v
nd_ddr2_port nd_ddr2_port - reusable access port to the Nexys 4 DDR's 128 MiB DDR2 fpga/nexys4ddr/ddr2/nd_ddr2_port.v
nd_ddr2_storage nd_ddr2_storage - the nd_storage region, held in DDR2 fpga/nexys4ddr/ddr2/nd_ddr2_storage.v
nd_memtest_bram ND-120 memory-path test as a character stream fpga/nexys4ddr/sd-fat-test/nd_memtest_bram.v
nd_memtest_ddr2 DDR2 memory test for the Nexys 4 DDR, as a character stream fpga/nexys4ddr/sd-fat-test/nd_memtest_ddr2.v
nd_memtest_mux Dispatcher for the SD-FAT test's external memory commands fpga/nexys4ddr/sd-fat-test/nd_memtest_mux.v
nexys4ddr_sd_fat_top Nexys 4 DDR wrapper for the SD-FAT test (sd_fat_test_top) fpga/nexys4ddr/sd-fat-test/nexys4ddr_sd_fat_top.v
SevenSegDebug8 8-digit 7-segment multiplexer for the Nexys 4 DDR fpga/nexys4ddr/SevenSegDebug8.v

FPGA board: qmtech-a35t

Module What it is Source
led_test_top - fpga/qmtech-a35t/led-test/led_test_top.v
nd120_qmtech_top QMTECH XC7A35T SDRAM core board - ND-120 top level fpga/qmtech-a35t/rtl/nd120_qmtech_top.v
nd_storage_bram nd_storage_bram - the nd_storage region, held in block RAM fpga/qmtech-a35t/rtl/nd_storage_bram.v
qmtech_mem_test_top QMTECH XC7A35T standalone memory test for the ND-120 BRAM path fpga/qmtech-a35t/mem-test/qmtech_mem_test_top.v

FPGA board: tang-nano-20k

Module What it is Source
buf_text_printer Raw text printer for the SD-FAT test fpga/tang-nano-20k/sd-fat-test/src/buf_text_printer.v
hex_dumper Hex/octal dumper for the SD-FAT test fpga/tang-nano-20k/sd-fat-test/src/hex_dumper.v
MEM_RAM_49_SDRAM MEM/RAM - SDRAM backend (Tang Nano 20K) fpga/tang-nano-20k/sdram-bridge/MEM_RAM_49_SDRAM.v
msg_printer UART message printer for the SDRAM test fpga/tang-nano-20k/sdram-test/src/msg_printer.v
msg_printer18 UART message printer for the sdram18 test fpga/tang-nano-20k/sdram18-test/src/msg_printer18.v
ND120_TANG20K_TOP TOP LEVEL FOR THE TANG NANO 20K (Gowin GW2AR-18) fpga/tang-nano-20k/src/ND120_TANG20K_TOP.v
sd_fat_test_top Tang Nano 20K SD + FAT test (Milestone 1 of the SD-BPUN device plan) fpga/tang-nano-20k/sd-fat-test/src/sd_fat_test_top.v
sdram - fpga/tang-nano-20k/sdram-test/src/sdram.v
sdram18 - fpga/tang-nano-20k/sdram-bridge/sdram18.v
sdram18_test_top Tang Nano 20K - sdram18.v hardware validation test fpga/tang-nano-20k/sdram18-test/src/sdram18_test_top.v
sdram_test_top Tang Nano 20K embedded-SDRAM test fpga/tang-nano-20k/sdram-test/src/sdram_test_top.v
status_printer Status message printer for the SD-FAT test fpga/tang-nano-20k/sd-fat-test/src/status_printer.v
uart_rx UART receiver (8N1) fpga/tang-nano-20k/sd-fat-test/src/uart_rx.v
uart_rx UART receiver (8N1) fpga/tang-nano-20k/sdram-test/src/uart_rx.v
uart_tx UART transmitter (8N1) fpga/tang-nano-20k/sd-fat-test/src/uart_tx.v
uart_tx UART transmitter (8N1) fpga/tang-nano-20k/sdram-test/src/uart_tx.v