FullAdder¶
Source: Verilog/Shared/logisim/FullAdder.v
Hierarchy: not instantiated by any of the 9 build tops (elaborated by yosys).
Module hierarchy - All modules
Schematic¶
Drawn from the Verilog: no build top uses this module, so it was elaborated from its own file with no defines and default parameters. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).
Description¶
Logisim-evolution goes FPGA automatic generated Verilog code https://github.com/logisim-evolution/ Component : FullAdder
Ports¶
| Direction | Width | Name | Description |
|---|---|---|---|
| input | 1 |
carryIn |
|
| output | 1 |
carryOut |
|
| input | 1 |
dataA |
|
| input | 1 |
dataB |
|
| output | 1 |
result |
Verilog source¶
Verilog/Shared/logisim/FullAdder.v on GitHub.
Show the Verilog of FullAdder (45 lines)
/******************************************************************************
** Logisim-evolution goes FPGA automatic generated Verilog code **
** https://github.com/logisim-evolution/ **
** **
** Component : FullAdder **
** **
*****************************************************************************/
module FullAdder( carryIn,
carryOut,
dataA,
dataB,
result );
/*******************************************************************************
** Here all module parameters are defined with a dummy value **
*******************************************************************************/
parameter extendedBits = 1;
/*******************************************************************************
** The inputs are defined here **
*******************************************************************************/
input carryIn;
input dataA;
input dataB;
/*******************************************************************************
** The outputs are defined here **
*******************************************************************************/
output carryOut;
output result;
/*******************************************************************************
** The wires are defined here **
*******************************************************************************/
wire [extendedBits-1:0] s_extendedDataA;
wire [extendedBits-1:0] s_extendedDataB;
wire [extendedBits-1:0] s_sumResult;
/*******************************************************************************
** The module functionality is described here **
*******************************************************************************/
assign {carryOut, result} = dataA + dataB + carryIn;
endmodule