AND_GATE_5_INPUTS¶
Source: Verilog/Shared/logisim/AND_GATE_5_INPUTS.v
Hierarchy: not instantiated by any of the 9 build tops (elaborated by yosys).
Module hierarchy - All modules
Schematic¶
Drawn from the Verilog: no build top uses this module, so it was elaborated from its own file with no defines and default parameters. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).
Description¶
Logisim-evolution goes FPGA automatic generated Verilog code https://github.com/logisim-evolution/ Component : AND_GATE_5_INPUTS
Ports¶
| Direction | Width | Name | Description |
|---|---|---|---|
| input | 1 |
input1 |
|
| input | 1 |
input2 |
|
| input | 1 |
input3 |
|
| input | 1 |
input4 |
|
| input | 1 |
input5 |
|
| output | 1 |
result |
Verilog source¶
Verilog/Shared/logisim/AND_GATE_5_INPUTS.v on GitHub.
Show the Verilog of AND_GATE_5_INPUTS (66 lines)
/******************************************************************************
** Logisim-evolution goes FPGA automatic generated Verilog code **
** https://github.com/logisim-evolution/ **
** **
** Component : AND_GATE_5_INPUTS **
** **
*****************************************************************************/
module AND_GATE_5_INPUTS( input1,
input2,
input3,
input4,
input5,
result );
/*******************************************************************************
** Here all module parameters are defined with a dummy value **
*******************************************************************************/
parameter [64:0] BubblesMask = 1;
/*******************************************************************************
** The inputs are defined here **
*******************************************************************************/
input input1;
input input2;
input input3;
input input4;
input input5;
/*******************************************************************************
** The outputs are defined here **
*******************************************************************************/
output result;
/*******************************************************************************
** The wires are defined here **
*******************************************************************************/
wire s_realInput1;
wire s_realInput2;
wire s_realInput3;
wire s_realInput4;
wire s_realInput5;
/*******************************************************************************
** The module functionality is described here **
*******************************************************************************/
/*******************************************************************************
** Here the bubbles are processed **
*******************************************************************************/
assign s_realInput1 = (BubblesMask[0] == 1'b0) ? input1 : ~input1;
assign s_realInput2 = (BubblesMask[1] == 1'b0) ? input2 : ~input2;
assign s_realInput3 = (BubblesMask[2] == 1'b0) ? input3 : ~input3;
assign s_realInput4 = (BubblesMask[3] == 1'b0) ? input4 : ~input4;
assign s_realInput5 = (BubblesMask[4] == 1'b0) ? input5 : ~input5;
/*******************************************************************************
** Here the functionality is defined **
*******************************************************************************/
assign result = s_realInput1&
s_realInput2&
s_realInput3&
s_realInput4&
s_realInput5;
endmodule