Comparator

Source: Verilog/Shared/logisim/Comparator.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_MIC > CMP4 > Comparator - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.MIC.LC_CMP.ARITH_1

Used in: CMP4 (all tops)

Contains: no other modules.

Module hierarchy - All modules

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.MIC.LC_CMP.ARITH_1. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description

ND120 Shared Component: Comparator Last reviewed: 2-FEB-2025 Ronny Hansen

Ports

Direction	Width	Name	Description
output	1	aEqualsB
output	1	aGreaterThanB
output	1	aLessThanB
input	[nrOfBits-1:0]	dataA
input	[nrOfBits-1:0]	dataB

Verilog source

Verilog/Shared/logisim/Comparator.v on GitHub.

Show the Verilog of Comparator (70 lines)

/**************************************************************************
** ND120 Shared                                                          **
**                                                                       **
** Component: Comparator                                                 **
**                                                                       **
** Last reviewed: 2-FEB-2025                                             **
** Ronny Hansen                                                          **
***************************************************************************/

module Comparator( aEqualsB,
                   aGreaterThanB,
                   aLessThanB,
                   dataA,
                   dataB );

   /*******************************************************************************
   ** Here all module parameters are defined with a dummy value                  **
   *******************************************************************************/
   parameter nrOfBits = 1;
   parameter twosComplement = 1;

   /*******************************************************************************
   ** The inputs are defined here                                                **
   *******************************************************************************/
   input [nrOfBits-1:0] dataA;
   input [nrOfBits-1:0] dataB;

   /*******************************************************************************
   ** The outputs are defined here                                               **
   *******************************************************************************/
   output aEqualsB;
   output aGreaterThanB;
   output aLessThanB;

   /*******************************************************************************
   ** The wires are defined here                                                 **
   *******************************************************************************/
   wire s_signedGreater;
   wire s_signedLess;
   wire s_unsignedGreater;
   wire s_unsignedLess;

   /*******************************************************************************
   ** The module functionality is described here                                 **
   *******************************************************************************/
   assign s_signedLess      = ($signed(dataA) < $signed(dataB));
   assign s_unsignedLess    = (dataA < dataB);
   assign s_signedGreater   = ($signed(dataA) > $signed(dataB));
   assign s_unsignedGreater = (dataA > dataB);

   assign aEqualsB      = (dataA == dataB);
   assign aGreaterThanB = (twosComplement==1) ? s_signedGreater : s_unsignedGreater;
   assign aLessThanB    = (twosComplement==1) ? s_signedLess : s_unsignedLess;


    /*******************************************************************************
    ** Prevent linter warnings for unused signals
    *******************************************************************************/
   generate
    if (twosComplement == 1)
      begin : gen_unused_unsigned
         (* keep = "true", DONT_TOUCH = "true" *) wire _unused = &{1'b0, s_unsignedGreater, s_unsignedLess};
      end
   else
      begin : gen_unused_signed
         (* keep = "true", DONT_TOUCH = "true" *) wire _unused = &{1'b0, s_signedGreater, s_signedLess};
      end
   endgenerate

endmodule