Multiplexer_2¶

Source: Verilog/Shared/logisim/Multiplexer_2.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_ALU > MUX21LP > Multiplexer_2 - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.ALU.AARG0_MUX.PLEXERS_1

Used in: CGA_MIC_CSEL (all tops), CGA_MIC_INCOUNT (all tops), MUX21L (all tops), MUX21LP (all tops), MUX24P (all tops)

Contains: no other modules.

Module hierarchy - All modules

Multiplexer_2 symbol

Schematic¶

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.ALU.AARG0_MUX.PLEXERS_1. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description¶

Component : Multiplexer_2 Refactored 03.12.2023 Ronny Hansen

Ports¶

Direction	Width	Name
input	`1`	`muxIn_1`
input	`1`	`sel`
output	`1`	`muxOut`

Verilog source¶

Verilog/Shared/logisim/Multiplexer_2.v on GitHub.

Show the Verilog of Multiplexer_2 (18 lines)

/******************************************************************************
 **                                                                          **
 ** Component : Multiplexer_2                                                **
 **                                                                          **
 ** Refactored 03.12.2023 Ronny Hansen                                       **
 *****************************************************************************/
/* */

module Multiplexer_2( input muxIn_0,
                      input muxIn_1,                      
                      input sel,
                      output wire muxOut
                      );   

      // Logic for 2-to-1 Multiplexer
    assign muxOut = sel ? muxIn_1 : muxIn_0;

endmodule