Multiplexer_bus_2¶

Source: Verilog/Shared/logisim/Multiplexer_bus_2.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_INTR > CGA_INTR_CNTLR > Multiplexer_bus_2 - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.INTR.CNTLR.PLEXERS_1

Used in: CGA_INTR_CNTLR (all tops)

Contains: no other modules.

Module hierarchy - All modules

Multiplexer_bus_2 symbol

Schematic¶

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.INTR.CNTLR.PLEXERS_1. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description¶

Component : Multiplexer_bus_2

Ports¶

Direction	Width	Name
input	`[nrOfBits-1:0]`	`muxIn_0`
input	`[nrOfBits-1:0]`	`muxIn_1`
input	`1`	`sel`
output	`[nrOfBits-1:0]`	`muxOut`

Verilog source¶

Verilog/Shared/logisim/Multiplexer_bus_2.v on GitHub.

Show the Verilog of Multiplexer_bus_2 (23 lines)

/******************************************************************************
 **                                                                          **
 ** Component : Multiplexer_bus_2                                            **
 **                                                                          **
 *****************************************************************************/

module Multiplexer_bus_2( muxIn_0, muxIn_1, sel, muxOut );

    // Parameters are declared here
    parameter nrOfBits = 1;

    // Inputs using the parameters in their declarations
    input [nrOfBits-1:0] muxIn_0;
    input [nrOfBits-1:0] muxIn_1;
    input sel;

    // Output using the parameters in its declaration
    output [nrOfBits-1:0] muxOut;

    // Logic for the 2-to-1 multiplexer bus
    assign muxOut = (sel == 1'b0) ? muxIn_0 : muxIn_1;

endmodule