XNOR_GATE_ONEHOT

Source: Verilog/Shared/logisim/XNOR_GATE_ONEHOT.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_MIC > CGA_MIC_INCOUNT > XNOR_GATE_ONEHOT - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.MIC.MIC_INCOUNT.GATES_3

Used in: CGA_INTR_CNTLR_IRQ_MASK_MASKBIT (all tops), CGA_INTR_CNTLR_VECGEN_STAT (all tops), CGA_MIC_CONDREG (all tops), CGA_MIC_INCOUNT (all tops)

Contains: no other modules.

Module hierarchy - All modules

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.MIC.MIC_INCOUNT.GATES_3. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description

Logisim-evolution goes FPGA automatic generated Verilog code https://github.com/logisim-evolution/ Component : XNOR_GATE_ONEHOT

Ports

Direction	Width	Name	Description
input	1	input1
input	1	input2
output	1	result

Verilog source

Verilog/Shared/logisim/XNOR_GATE_ONEHOT.v on GitHub.

Show the Verilog of XNOR_GATE_ONEHOT (52 lines)

/******************************************************************************
 ** Logisim-evolution goes FPGA automatic generated Verilog code             **
 ** https://github.com/logisim-evolution/                                    **
 **                                                                          **
 ** Component : XNOR_GATE_ONEHOT                                             **
 **                                                                          **
 *****************************************************************************/

module XNOR_GATE_ONEHOT( input1,
                         input2,
                         result );

   /*******************************************************************************
   ** Here all module parameters are defined with a dummy value                  **
   *******************************************************************************/
   parameter [64:0] BubblesMask = 1;

   /*******************************************************************************
   ** The inputs are defined here                                                **
   *******************************************************************************/
   input input1;
   input input2;

   /*******************************************************************************
   ** The outputs are defined here                                               **
   *******************************************************************************/
   output result;

   /*******************************************************************************
   ** The wires are defined here                                                 **
   *******************************************************************************/
   wire s_realInput1;
   wire s_realInput2;

   /*******************************************************************************
   ** The module functionality is described here                                 **
   *******************************************************************************/

   /*******************************************************************************
   ** Here the bubbles are processed                                             **
   *******************************************************************************/
   assign  s_realInput1 = (BubblesMask[0] == 1'b0) ? input1 : ~input1;
   assign  s_realInput2 = (BubblesMask[1] == 1'b0) ? input2 : ~input2;

   /*******************************************************************************
   ** Here the functionality is defined                                          **
   *******************************************************************************/
   assign result = ~((s_realInput1&~(s_realInput2))|
                     (~(s_realInput1)&s_realInput2));


endmodule