Multiplexer_4¶

Source: Verilog/Shared/logisim/Multiplexer_4.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_MIC > MUX34P > Multiplexer_4 - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.MIC.ILC_MUX.PLEXERS_1

Used in: CGA_MIC_IPOS (all tops), CGA_TRAP_TVGEN_P2 (all tops), MUX31LP (all tops), MUX34P (all tops), MUX41P (all tops)

Contains: no other modules.

Module hierarchy - All modules

Multiplexer_4 symbol

Schematic¶

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.MIC.ILC_MUX.PLEXERS_1. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description¶

Component : Multiplexer_4 Functionality: 4-to-1 multiplexer Refactored 03.12.2023 Ronny Hansen

Ports¶

Direction	Width	Name
input	`1`	`muxIn_0`
input	`1`	`muxIn_1`
input	`1`	`muxIn_2`
input	`1`	`muxIn_3`
input	`[1:0]`	`sel`
output	`1`	`muxOut`

Verilog source¶

Verilog/Shared/logisim/Multiplexer_4.v on GitHub.

Show the Verilog of Multiplexer_4 (27 lines)

/******************************************************************************
 **                                                                          **
 ** Component : Multiplexer_4                                                **
 ** Functionality: 4-to-1 multiplexer                                        **
 ** Refactored 03.12.2023 Ronny Hansen                                       **
 *****************************************************************************/

module Multiplexer_4(
    input wire muxIn_0,
    input wire muxIn_1,
    input wire muxIn_2,
    input wire muxIn_3,
    input wire [1:0] sel,
    output reg muxOut
);

    // Combinational logic to select the output based on 'sel'
    always @(*) begin
        case(sel)
            2'b00: muxOut = muxIn_0; // Select input 0
            2'b01: muxOut = muxIn_1; // Select input 1
            2'b10: muxOut = muxIn_2; // Select input 2
            2'b11: muxOut = muxIn_3; // Select input 3
            default: muxOut = 1'bx;  // Undefined state
        endcase
    end
endmodule