Multiplexer_2_w_enable¶

Source: Verilog/Shared/logisim/Multiplexer_2_w_enable.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > IO_37 > IO_DCD_38 > DECODE_DGA > DECODE_DGA_POW > F571 > Multiplexer_2_w_enable - instance path: CORE.CPU_BOARD.IO.DCD.DGA.POW.A620.PLEXERS_1

Used in: F571 (all tops)

Contains: no other modules.

Module hierarchy - All modules

Multiplexer_2_w_enable symbol

Schematic¶

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.IO.DCD.DGA.POW.A620.PLEXERS_1. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description¶

Component : Multiplexer_2_w_enable Refactored 03.12.2023 Ronny Hansen

Ports¶

Direction	Width	Name
input	`1`	`muxIn_0`
input	`1`	`muxIn_1`
input	`1`	`sel`
output	`1`	`muxOut`

Verilog source¶

Verilog/Shared/logisim/Multiplexer_2_w_enable.v on GitHub.

Show the Verilog of Multiplexer_2_w_enable (16 lines)

/******************************************************************************
 **                                                                          **
 ** Component : Multiplexer_2_w_enable                                       **
 **                                                                          **
 ** Refactored 03.12.2023 Ronny Hansen                                       **
 *****************************************************************************/
/* */

module Multiplexer_2_w_enable( input wire enable,
                      input wire muxIn_0,
                      input wire muxIn_1,                      
                      input wire sel,
                      output wire muxOut
                      );   
      assign muxOut = (enable == 1'b0) ? 1'b0 : (sel ? muxIn_1 : muxIn_0);
endmodule