D_FLIPFLOP_EN¶
Source: Verilog/Shared/ndlib/D_FLIPFLOP_EN.v
Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > IO_37 > IO_DCD_38 > DECODE_DGA > DECODE_DGA_COMM > D_FLIPFLOP_EN
- instance path: CORE.CPU_BOARD.IO.DCD.DGA.COMM.MEMORY_63
Used in: CGA_ALU (all tops), CGA_ALU_GPR (all tops), CGA_CPU_ALU_CONTR (all tops), CGA_DCD (all tops), CGA_INTR (all tops), CGA_INTR_CNTLR_IRGEL_HIGEL (all tops), CGA_INTR_CNTLR_IRGEL_LOGEL (all tops), CGA_INTR_CNTLR_IRQ_MASK_MASKBIT (all tops), CGA_INTR_CNTLR_IRQ_REG_RQBIT_V2 (all tops), CGA_INTR_CNTLR_MDCD (all tops), CGA_INTR_CNTLR_VECGEN_STAT_SBIT (all tops), CGA_MAC_LASEL (all tops), CGA_MIC (all tops), CGA_MIC_INCOUNT (all tops), CGA_MIC_STACK_BIT (all tops), CGA_MIC_STACK_BIT12 (all tops), CGA_TRAP_TVGEN_P2 (all tops), DECODE_DGA_COMM (all tops), F924_EN (all tops), M169C_EN (all tops)
Contains: no other modules.
Module hierarchy - All modules
Schematic¶
Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.IO.DCD.DGA.COMM.MEMORY_63. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).
Description¶
ND120 Shared
D_FLIPFLOP_EN - D_FLIPFLOP with an optional clock-enable mode.
USE_ENABLE=0 (default): wraps the original D_FLIPFLOP - posedge
clock, original behaviour.
USE_ENABLE=1: posedge sysclk, captures when EN is high (P2 clock-
domain conversion mode - see SCAN_FF_EN.v / the plan doc).
USE_ENABLE=2: strobe edge-capture - clock carries a control strobe,
not a clock; capture d on a sysclk-detected rise of clock (P3
mode, AM29C821 USE_SYSCLK=2 pattern). EN is unused (tie 0).
ASYNC_RESET=0 (default): preset/reset must be tied 0 (clean sync
flop, InvertClockEnable=0).
ASYNC_RESET=1: preset/reset are async active-high set/clear with
preset priority, like the original D_FLIPFLOP with ACTIVE_ASYNC(1).
tick is unused (tie 1).
Last reviewed: 10-JUL-2026
Ronny Hansen
Parameters¶
| Parameter | Default |
|---|---|
USE_ENABLE |
0 |
ASYNC_RESET |
0 |
Ports¶
| Direction | Width | Name | Description |
|---|---|---|---|
| input | 1 |
sysclk |
FPGA system clock (used only when USE_ENABLE=1) |
| input | 1 |
EN |
Clock enable (used only when USE_ENABLE=1) |
| input | 1 |
clock |
Clock (used only when USE_ENABLE=0) |
| input | 1 |
d |
D input |
| input | 1 |
preset |
Must be tied 0 |
| input | 1 |
reset |
Async active-high clear when ASYNC_RESET=1, else tie 0 |
| input | 1 |
tick |
Not used (tie 1) |
| output | 1 |
q |
|
| output | 1 |
qBar |
Verilog source¶
Verilog/Shared/ndlib/D_FLIPFLOP_EN.v on GitHub.
Show the Verilog of D_FLIPFLOP_EN (112 lines)
/**************************************************************************
** ND120 Shared **
** **
** D_FLIPFLOP_EN - D_FLIPFLOP with an optional clock-enable mode. **
** **
** USE_ENABLE=0 (default): wraps the original D_FLIPFLOP - posedge **
** clock, original behaviour. **
** USE_ENABLE=1: posedge sysclk, captures when EN is high (P2 clock- **
** domain conversion mode - see SCAN_FF_EN.v / the plan doc). **
** USE_ENABLE=2: strobe edge-capture - `clock` carries a control strobe, **
** not a clock; capture d on a sysclk-detected rise of `clock` (P3 **
** mode, AM29C821 USE_SYSCLK=2 pattern). EN is unused (tie 0). **
** **
** ASYNC_RESET=0 (default): preset/reset must be tied 0 (clean sync **
** flop, InvertClockEnable=0). **
** ASYNC_RESET=1: preset/reset are async active-high set/clear with **
** preset priority, like the original D_FLIPFLOP with ACTIVE_ASYNC(1). **
** **
** tick is unused (tie 1). **
** **
** Last reviewed: 10-JUL-2026 **
** Ronny Hansen **
***************************************************************************/
module D_FLIPFLOP_EN #(
parameter integer USE_ENABLE = 0,
parameter integer ASYNC_RESET = 0
) (
input sysclk, //! FPGA system clock (used only when USE_ENABLE=1)
input EN, //! Clock enable (used only when USE_ENABLE=1)
input clock, //! Clock (used only when USE_ENABLE=0)
input d, //! D input
input preset, //! Must be tied 0
input reset, //! Async active-high clear when ASYNC_RESET=1, else tie 0
//! (preset likewise an async set, priority over reset)
input tick, //! Not used (tie 1)
output q,
output qBar
);
generate
if (USE_ENABLE == 1 && ASYNC_RESET == 1) begin : gen_enable_arst
/* verilator lint_off UNUSEDSIGNAL */
wire unused = clock & tick;
/* verilator lint_on UNUSEDSIGNAL */
reg q_r = 1'b0;
always @(posedge sysclk or posedge preset or posedge reset) begin
if (preset) q_r <= 1'b1;
else if (reset) q_r <= 1'b0;
else if (EN) q_r <= d;
end
assign q = q_r;
assign qBar = ~q_r;
end else if (USE_ENABLE == 2) begin : gen_strobe_edge
/* verilator lint_off UNUSEDSIGNAL */
wire unused = EN & preset & reset & tick;
/* verilator lint_on UNUSEDSIGNAL */
reg q_r = 1'b0;
reg clock_d = 1'b0;
always @(posedge sysclk) begin
clock_d <= clock;
if (clock && !clock_d) q_r <= d;
end
assign q = q_r;
assign qBar = ~q_r;
end else if (USE_ENABLE == 1) begin : gen_enable
/* verilator lint_off UNUSEDSIGNAL */
wire unused = clock & preset & reset & tick;
/* verilator lint_on UNUSEDSIGNAL */
reg q_r = 1'b0;
always @(posedge sysclk) begin
if (EN) q_r <= d;
end
assign q = q_r;
assign qBar = ~q_r;
end else if (ASYNC_RESET == 1) begin : gen_orig_arst
/* verilator lint_off UNUSEDSIGNAL */
wire unused_sys = sysclk & EN;
/* verilator lint_on UNUSEDSIGNAL */
D_FLIPFLOP #(
.ACTIVE_ASYNC(1),
.InvertClockEnable(0)
) FF (
.clock (clock),
.d (d),
.preset(preset),
.reset (reset),
.tick (tick),
.q (q),
.qBar (qBar)
);
end else begin : gen_orig
/* verilator lint_off UNUSEDSIGNAL */
wire unused_sys = sysclk & EN;
/* verilator lint_on UNUSEDSIGNAL */
D_FLIPFLOP #(
.InvertClockEnable(0)
) FF (
.clock (clock),
.d (d),
.preset(preset),
.reset (reset),
.tick (tick),
.q (q),
.qBar (qBar)
);
end
endgenerate
endmodule