MUX21LP¶

Source: Verilog/Shared/ndlib/MUX21LP.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_ALU > MUX21LP - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.ALU.AARG0_MUX

Used in: CGA_ALU (all tops), CGA_ALU_GPR (all tops), CGA_ALU_RALU_MUX216L (all tops), CGA_CPU_ALU_CONTR (all tops)

Contains: Multiplexer_2

Module hierarchy - All modules

MUX21LP symbol

Schematic¶

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.ALU.AARG0_MUX. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description¶

Component : MUX21LP (2-to-1 Multiplexer NEGATED)

Ports¶

Direction	Width	Name	Description
input	`1`	`A`	Input A
input	`1`	`B`	Input B
input	`1`	`S`	Select input
output	`1`	`ZN`	Negated Output

Verilog source¶

Verilog/Shared/ndlib/MUX21LP.v on GitHub.

Show the Verilog of MUX21LP (25 lines)

/******************************************************************************
 **                                                                          **
 ** Component : MUX21LP  (2-to-1 Multiplexer NEGATED)                                                     **
 **                                                                          **
 *****************************************************************************/

module MUX21LP( 
   input A,    // Input A
   input B,    // Input B
   input S,    // Select input
   output ZN   // Negated Output
   );

   wire wire_plexer_out;
   assign ZN = ~wire_plexer_out;

   Multiplexer_2   PLEXERS_1 (
                              .muxIn_0(A),
                              .muxIn_1(B),
                              .muxOut(wire_plexer_out),
                              .sel(S)
   );


endmodule