J_K_FLIPFLOP

Source: Verilog/Shared/logisim/J_K_FLIPFLOP.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > IO_37 > IO_DCD_38 > DECODE_DGA > DECODE_DGA_POW > J_K_FLIPFLOP - instance path: CORE.CPU_BOARD.IO.DCD.DGA.POW.A616

Used in: DECODE_DGA_POW (all tops)

Contains: no other modules.

Module hierarchy - All modules

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.IO.DCD.DGA.POW.A616. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description

ND120 SHARED CODE J-K FLIP-FLOP Last reviewed: 11-NOV-2024 Ronny Hansen

Parameters

Parameter	Default
InvertClockEnable	1

Ports

Direction	Width	Name	Description
input	1	clock
input	1	j
input	1	k
input	1	preset
input	1	reset
input	1	tick
output	1	q
output	1	qBar

Verilog source

Verilog/Shared/logisim/J_K_FLIPFLOP.v on GitHub.

Show the Verilog of J_K_FLIPFLOP (47 lines)

/**************************************************************************
** ND120 SHARED CODE                                                     **
** J-K FLIP-FLOP                                                         **
**                                                                       **
**                                                                       **
** Last reviewed: 11-NOV-2024                                            **
** Ronny Hansen                                                          **
***************************************************************************/

module J_K_FLIPFLOP #(
    parameter integer InvertClockEnable = 1
) (
    input  clock,
    input  j,
    input  k,
    input  preset,
    input  reset,
    input  tick,
    output q,
    output qBar
);

  reg s_currentState;

  // Output logic
  assign q = s_currentState;
  assign qBar = ~s_currentState;

  // Clock inversion based on parameter
  wire s_clock = (InvertClockEnable == 0) ? clock : ~clock;

  // State transition logic
  wire s_nextState = (~s_currentState & j) | (s_currentState & ~k);

  // State update logic
  //always @(posedge reset or posedge preset or posedge s_clock) begin (Vivado doesnt like ASYNC RESET )
  always @(posedge s_clock) begin
    if (preset)  // priority to pre-set
      s_currentState <= 1'b1;
    else if (reset) s_currentState <= 1'b0;
    else if (tick) s_currentState <= s_nextState;
  end

  // Initial state for simulation
  initial s_currentState = 0;

endmodule