SCAN_FF_EN

Source: Verilog/Shared/ndlib/SCAN_FF_EN.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_DCD > SCAN_FF_EN - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.DCD.CFETCH_FF

Used in: CGA_ALU_DBR (all tops), CGA_ALU_GPR (all tops), CGA_ALU_STS (all tops), CGA_DCD (all tops), CGA_IDBCTL_PGSREG (all tops), CGA_INTR_CNTLR_IRGEL_HIRL (all tops), CGA_INTR_CNTLR_IRGEL_LORL (all tops), CGA_INTR_CNTLR_VECGEN_VHR (all tops), CGA_MIC_CONDREG (all tops), CGA_MIC_WCAREG (all tops)

Contains: no other modules.

Module hierarchy - All modules

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.DCD.CFETCH_FF. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description

ND120 Shared SCAN_FF_EN - SCAN_FF with an optional clock-enable mode. USE_ENABLE=0 (default): wraps the original SCAN_FF - clocked on posedge CLK, bit-for-bit the original behaviour (latch mode). USE_ENABLE=1: clocked on posedge sysclk, captures when EN is high. For the P2 clock-domain conversions (docs/ plan-fix-unconstrained-clocks.md): EN is a CYC_36 *_EN pulse aligned so the capture lands on the same edge the phase-accurate clock rises - the CLK pin is unused in this mode and the flop lives in the sysclk domain (constrained, retimable, no fabric- routed clock). Last reviewed: 9-JUL-2026 Ronny Hansen

Parameters

Parameter	Default
USE_ENABLE	0

Ports

Direction	Width	Name	Description
input	1	sysclk	FPGA system clock (used only when USE_ENABLE=1)
input	1	EN	Clock enable (used only when USE_ENABLE=1)
input	1	CLK	Clock (positive triggered; used only when USE_ENABLE=0)
input	1	D	D input
input	1	TE	T enable
input	1	TI	T Input
output	1	Q	Q output
output	1	QN	Q_n output

Verilog source

Verilog/Shared/ndlib/SCAN_FF_EN.v on GitHub.

Show the Verilog of SCAN_FF_EN (61 lines)

/**************************************************************************
** ND120 Shared                                                          **
**                                                                       **
** SCAN_FF_EN - SCAN_FF with an optional clock-enable mode.              **
**                                                                       **
** USE_ENABLE=0 (default): wraps the original SCAN_FF - clocked on       **
**   posedge CLK, bit-for-bit the original behaviour (latch mode).       **
** USE_ENABLE=1: clocked on posedge sysclk, captures when EN is high.    **
**   For the P2 clock-domain conversions (docs/                          **
**   plan-fix-unconstrained-clocks.md): EN is a CYC_36 *_EN pulse        **
**   aligned so the capture lands on the same edge the phase-accurate    **
**   clock rises - the CLK pin is unused in this mode and the flop       **
**   lives in the sysclk domain (constrained, retimable, no fabric-      **
**   routed clock).                                                      **
**                                                                       **
** Last reviewed: 9-JUL-2026                                             **
** Ronny Hansen                                                          **
***************************************************************************/

module SCAN_FF_EN #(
    parameter integer USE_ENABLE = 0
) (
    input sysclk,  //! FPGA system clock (used only when USE_ENABLE=1)
    input EN,      //! Clock enable    (used only when USE_ENABLE=1)

    input CLK,  //! Clock (positive triggered; used only when USE_ENABLE=0)
    input D,    //! D input
    input TE,   //! T enable
    input TI,   //! T Input

    output Q,  //! Q output
    output QN  //! Q_n output
);

  generate
    if (USE_ENABLE == 1) begin : gen_enable
      /* verilator lint_off UNUSEDSIGNAL */
      wire unused_clk = CLK;
      /* verilator lint_on UNUSEDSIGNAL */
      reg q_r = 1'b0;
      always @(posedge sysclk) begin
        if (EN) q_r <= TE ? TI : D;
      end
      assign Q  = q_r;
      assign QN = ~q_r;
    end else begin : gen_orig
      /* verilator lint_off UNUSEDSIGNAL */
      wire unused_sys = sysclk & EN;
      /* verilator lint_on UNUSEDSIGNAL */
      SCAN_FF FF (
          .CLK(CLK),
          .D  (D),
          .TE (TE),
          .TI (TI),
          .Q  (Q),
          .QN (QN)
      );
    end
  endgenerate

endmodule