Adder

Source: Verilog/Shared/logisim/Adder.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_MAC > CGA_MAC_ADD > CGA_MAC_FASTADD > Adder - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.MAC.MAC_ADD.FASTADD.ARITH_1

Used in: CGA_CPU_ALU_RALU (all tops), CGA_MAC_FASTADD (all tops)

Contains: no other modules.

Module hierarchy - All modules

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.ALU.ALU_RALU.ARITH_12. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description

Component : Adder

Ports

Direction	Width	Name	Description
input	1	carryIn
output	1	carryOut
input	[nrOfBits-1:0]	dataA
input	[nrOfBits-1:0]	dataB
output	[nrOfBits-1:0]	result

Verilog source

Verilog/Shared/logisim/Adder.v on GitHub.

Show the Verilog of Adder (39 lines)

/******************************************************************************
 **                                                                          **
 ** Component : Adder                                                        **
 **                                                                          **
 *****************************************************************************/

module Adder( carryIn, carryOut, dataA, dataB, result );

   // Parameters are declared here
   parameter extendedBits = 1;
   parameter nrOfBits = 1;

   // Validate parameters
   initial begin
      if (nrOfBits <= 0) begin
         $display("Error: nrOfBits must be greater than 0.");
         $finish;
      end
      if (extendedBits <= 0) begin
         $display("Error: extendedBits must be greater than 0.");
         $finish;
      end
   end

   // Inputs using the parameters in their declarations
   input carryIn;
   input [nrOfBits-1:0] dataA;
   input [nrOfBits-1:0] dataB;

   // Outputs using the parameters in their declarations
   output reg carryOut;
   output reg [nrOfBits-1:0] result;

   // Combinational logic for addition
   always @* begin
      {carryOut, result} = dataA + dataB + carryIn;
   end

endmodule