NAND_GATE

Source: Verilog/Shared/logisim/NAND_GATE.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > BIF_5 > BIF_BCTL_6 > NAND_GATE - instance path: CORE.CPU_BOARD.BIF.BCTL.GATES_1

Used in: BIF_BCTL_6 (all tops), BIF_BCTL_BDRV_7 (all tops), CGA_ALU_OUTMUX_IDBS (all tops), CGA_ALU_OUTMUX_SEL8 (all tops), CGA_ALU_STS (all tops), CGA_CPU_ALU_CONTR (all tops), CGA_CPU_ALU_OUTMUX_SEL7 (all tops), CGA_CPU_ALU_RALU (all tops), CGA_DCD (all tops), CGA_INTR_CNTLR_CLR_CLRBIT (all tops), CGA_INTR_CNTLR_IRGEL_HIGEL (all tops), CGA_INTR_CNTLR_IRGEL_HIRL (all tops), CGA_INTR_CNTLR_IRGEL_LOGEL (all tops), CGA_INTR_CNTLR_IRGEL_VMUX (all tops), CGA_INTR_CNTLR_IRQ_MASK_MASKBIT (all tops), CGA_INTR_CNTLR_IRQ_MREQ (all tops), CGA_INTR_CNTLR_MDCD (all tops), CGA_INTR_CNTLR_VECGEN_CMP_MAGCMP (all tops), CGA_INTR_CNTLR_VECGEN_ISMUX (all tops), CGA_INTR_CNTLR_VECGEN_OSMUX (all tops), CGA_INTR_CNTLR_VECGEN_PTY_PTYENC (all tops), CGA_INTR_IRSRC (all tops), CGA_MAC_ADD (all tops), CGA_MAC_AP09 (all tops), CGA_MAC_DECODE (all tops), CGA_MAC_LA1025 (all tops), CGA_MAC_LASEL (all tops), CGA_MAC_PTSEL (all tops), CGA_MIC (all tops), CGA_MIC_CONDREG (all tops), CGA_MIC_INCOUNT (all tops), CGA_MIC_IPOS (all tops), CGA_MIC_STACK (all tops), CGA_MIC_STACK_BIT (all tops), CGA_MIC_STACK_BIT12 (all tops), CGA_TESTMUX (all tops), CGA_TRAP_BRKDET (all tops), CGA_TRAP_TVGEN (all tops), CGA_TRAP_TVGEN_P2 (all tops), CGA_WRF (all tops), DECODE_DGA_COMM (all tops)

Contains: no other modules.

Module hierarchy - All modules

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.BIF.BCTL.GATES_1. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description

Logisim-evolution goes FPGA automatic generated Verilog code https://github.com/logisim-evolution/ Component : NAND_GATE

Ports

Direction	Width	Name	Description
input	1	input1
input	1	input2
output	1	result

Verilog source

Verilog/Shared/logisim/NAND_GATE.v on GitHub.

Show the Verilog of NAND_GATE (51 lines)

/******************************************************************************
 ** Logisim-evolution goes FPGA automatic generated Verilog code             **
 ** https://github.com/logisim-evolution/                                    **
 **                                                                          **
 ** Component : NAND_GATE                                                    **
 **                                                                          **
 *****************************************************************************/

module NAND_GATE( input1,
                  input2,
                  result );

   /*******************************************************************************
   ** Here all module parameters are defined with a dummy value                  **
   *******************************************************************************/
   parameter [64:0] BubblesMask = 1;

   /*******************************************************************************
   ** The inputs are defined here                                                **
   *******************************************************************************/
   input input1;
   input input2;

   /*******************************************************************************
   ** The outputs are defined here                                               **
   *******************************************************************************/
   output result;

   /*******************************************************************************
   ** The wires are defined here                                                 **
   *******************************************************************************/
   wire s_realInput1;
   wire s_realInput2;

   /*******************************************************************************
   ** The module functionality is described here                                 **
   *******************************************************************************/

   /*******************************************************************************
   ** Here the bubbles are processed                                             **
   *******************************************************************************/
   assign  s_realInput1 = (BubblesMask[0] == 1'b0) ? input1 : ~input1;
   assign  s_realInput2 = (BubblesMask[1] == 1'b0) ? input2 : ~input2;

   /*******************************************************************************
   ** Here the functionality is defined                                          **
   *******************************************************************************/
   assign result = ~(s_realInput1&
                     s_realInput2);

endmodule