RMUX_Gates

Source: Verilog/Shared/ndlib/RMUX_Gates.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_ALU > CGA_CPU_ALU_RMUX > RMUX_Gates - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.ALU.ALU_RMUX.RN15

Used in: CGA_CPU_ALU_RMUX (all tops)

Contains: AND_GATE x2, NOR_GATE

Module hierarchy - All modules

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.ALU.ALU_RMUX.RN15. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description

ND120 Shared Component : RMUX_Gates Last reviewed: 11-NOV-2024 Ronny Hansen

Ports

Direction	Width	Name	Description
input	1	A
input	1	D
input	1	RA
input	1	RD
output	1	RN

Verilog source

Verilog/Shared/ndlib/RMUX_Gates.v on GitHub.

Show the Verilog of RMUX_Gates (76 lines)

/**************************************************************************
** ND120 Shared                                                          **
**                                                                       **
** Component : RMUX_Gates                                                **
**                                                                       **
** Last reviewed: 11-NOV-2024                                            **
** Ronny Hansen                                                          **
***************************************************************************/


module RMUX_Gates (
    input A,
    input D,
    input RA,
    input RD,

    output RN
);

  /*******************************************************************************
   ** The wires are defined here                                                 **
   *******************************************************************************/
  wire s_gates1_out;
  wire s_gates2_out;
  wire s_rn_out;
  wire s_a;
  wire s_ra;
  wire s_d;
  wire s_rd;

  /*******************************************************************************
   ** The module functionality is described here                                 **
   *******************************************************************************/

  /*******************************************************************************
   ** Here all input connections are defined                                     **
   *******************************************************************************/
  assign s_a  = A;
  assign s_ra = RA;
  assign s_d  = D;
  assign s_rd = RD;

  /*******************************************************************************
   ** Here all output connections are defined                                    **
   *******************************************************************************/
  assign RN   = s_rn_out;

  /*******************************************************************************
   ** Here all normal components are defined                                     **
   *******************************************************************************/
  AND_GATE #(
      .BubblesMask(2'b00)
  ) GATES_1 (
      .input1(s_a),
      .input2(s_ra),
      .result(s_gates1_out)
  );

  AND_GATE #(
      .BubblesMask(2'b00)
  ) GATES_2 (
      .input1(s_d),
      .input2(s_rd),
      .result(s_gates2_out)
  );

  NOR_GATE #(
      .BubblesMask(2'b00)
  ) GATES_3 (
      .input1(s_gates1_out),
      .input2(s_gates2_out),
      .result(s_rn_out)
  );


endmodule