NAND_GATE_5_INPUTS

Source: Verilog/Shared/logisim/NAND_GATE_5_INPUTS.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > IO_37 > IO_DCD_38 > DECODE_DGA > DECODE_DGA_COMM > NAND_GATE_5_INPUTS - instance path: CORE.CPU_BOARD.IO.DCD.DGA.COMM.A150

Used in: CGA_ALU_OUTMUX_IDBS (all tops), CGA_DCD (all tops), CGA_MAC_APOS_CALCA (all tops), CGA_MAC_DECODE (all tops), CGA_MAC_LASEL (all tops), CGA_TRAP_TVGEN (all tops), CGA_TRAP_TVGEN_P2 (all tops), DECODE_DGA_COMM (all tops)

Contains: no other modules.

Module hierarchy - All modules

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.IO.DCD.DGA.COMM.A150. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description

Logisim-evolution goes FPGA automatic generated Verilog code https://github.com/logisim-evolution/ Component : NAND_GATE_5_INPUTS

Ports

Direction	Width	Name	Description
input	1	input1
input	1	input2
input	1	input3
input	1	input4
input	1	input5
output	1	result

Verilog source

Verilog/Shared/logisim/NAND_GATE_5_INPUTS.v on GitHub.

Show the Verilog of NAND_GATE_5_INPUTS (66 lines)

/******************************************************************************
 ** Logisim-evolution goes FPGA automatic generated Verilog code             **
 ** https://github.com/logisim-evolution/                                    **
 **                                                                          **
 ** Component : NAND_GATE_5_INPUTS                                           **
 **                                                                          **
 *****************************************************************************/

module NAND_GATE_5_INPUTS( input1,
                           input2,
                           input3,
                           input4,
                           input5,
                           result );

   /*******************************************************************************
   ** Here all module parameters are defined with a dummy value                  **
   *******************************************************************************/
   parameter [64:0] BubblesMask = 1;

   /*******************************************************************************
   ** The inputs are defined here                                                **
   *******************************************************************************/
   input input1;
   input input2;
   input input3;
   input input4;
   input input5;

   /*******************************************************************************
   ** The outputs are defined here                                               **
   *******************************************************************************/
   output result;

   /*******************************************************************************
   ** The wires are defined here                                                 **
   *******************************************************************************/
   wire s_realInput1;
   wire s_realInput2;
   wire s_realInput3;
   wire s_realInput4;
   wire s_realInput5;

   /*******************************************************************************
   ** The module functionality is described here                                 **
   *******************************************************************************/

   /*******************************************************************************
   ** Here the bubbles are processed                                             **
   *******************************************************************************/
   assign  s_realInput1 = (BubblesMask[0] == 1'b0) ? input1 : ~input1;
   assign  s_realInput2 = (BubblesMask[1] == 1'b0) ? input2 : ~input2;
   assign  s_realInput3 = (BubblesMask[2] == 1'b0) ? input3 : ~input3;
   assign  s_realInput4 = (BubblesMask[3] == 1'b0) ? input4 : ~input4;
   assign  s_realInput5 = (BubblesMask[4] == 1'b0) ? input5 : ~input5;

   /*******************************************************************************
   ** Here the functionality is defined                                          **
   *******************************************************************************/
   assign result = ~(s_realInput1&
                     s_realInput2&
                     s_realInput3&
                     s_realInput4&
                     s_realInput5);

endmodule