MUX41P¶

Source: Verilog/Shared/ndlib/MUX41P.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_MIC > MUX41P - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.MIC.M_LAA_3

Used in: CGA_ALU_GPR (all tops), CGA_ALU_QREG (all tops), CGA_ALU_RALU_LOGOP (all tops), CGA_ALU_SMUX (all tops), CGA_ALU_STS (all tops), CGA_CPU_ALU_CONTR (all tops), CGA_MIC (all tops)

Contains: Multiplexer_4

Module hierarchy - All modules

MUX41P symbol

Schematic¶

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.MIC.M_LAA_3. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description¶

Component : MUX41P

Ports¶

Direction	Width	Name
input	`1`	`A`
input	`1`	`B`
input	`1`	`D0`
input	`1`	`D1`
input	`1`	`D2`
input	`1`	`D3`
output	`1`	`Z`

Verilog source¶

Verilog/Shared/ndlib/MUX41P.v on GitHub.

Show the Verilog of MUX41P (26 lines)

/******************************************************************************
 **                                                                          **
 ** Component : MUX41P                                                       **
 **                                                                          **
 *****************************************************************************/

module MUX41P(A, B, D0, D1, D2, D3, Z);

   // Inputs
   input A, B, D0, D1, D2, D3;

   // Output
   output Z;

   // 4-to-1 Multiplexer
   Multiplexer_4 PLEXER (
      .muxIn_0(D0),
      .muxIn_1(D1),
      .muxIn_2(D2),
      .muxIn_3(D3),
      .muxOut(Z),
      .sel({B, A})
   );

endmodule