MUX31LP

Source: Verilog/Shared/ndlib/MUX31LP.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > CPU_15 > CPU_PROC_32 > CPU_PROC_CGA_33 > CGA > CGA_ALU > CGA_ALU_SHIFT > MUX31LP - instance path: CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.ALU.ALU_SHIFT.RB0MUX

Used in: CGA_ALU_OUTMUX (all tops), CGA_ALU_SHIFT (all tops), CGA_ALU_STS (all tops), CGA_WRF_RBLOCK_PREG (all tops)

Contains: Multiplexer_4

Module hierarchy - All modules

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.CPU.PROC.CGA.DELILAH.ALU.ALU_SHIFT.RB0MUX. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description

Component : MUX31LP Manually cleaned up from logisim generator that creates wires not used..

Ports

Direction	Width	Name	Description
input	1	B
input	1	D0
input	1	D1
input	1	D2
output	1	ZN

Verilog source

Verilog/Shared/ndlib/MUX31LP.v on GitHub.

Show the Verilog of MUX31LP (40 lines)

/******************************************************************************
 **                                                                          **
 ** Component : MUX31LP                                                      **
 **                                                                          **
 ** Manually cleaned up from logisim generator that creates wires not used.. **
 *****************************************************************************/

module MUX31LP( input A,
                input B,
                input D0,
                input D1,
                input D2,
                output ZN );

   wire [1:0] s_select;
   wire       s_d0;
   wire       s_d1;
   wire       s_d2;         

   wire       s_muxout;   

   assign s_select[0]   = A;
   assign s_select[1]   = B;
   assign s_d0          = D0;   
   assign s_d1          = D1;
   assign s_d2          = D2;

   assign ZN = ~s_muxout;


   Multiplexer_4   PLEXERS_1 (
                              .muxIn_0(s_d0),
                              .muxIn_1(s_d1),
                              .muxIn_2(s_d2),
                              .muxIn_3(s_d2),
                              .muxOut(s_muxout),
                              .sel(s_select[1:0]));


endmodule