PAL_45008B¶

Source: Verilog/PAL/PAL_45008B.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > MEM_43 > MEM_DATA_46 > PAL_45008B - instance path: CORE.CPU_BOARD.MEM.DATA.PAL_45008_UDATA

Used in: MEM_DATA_46 (all tops)

Contains: no other modules.

Module hierarchy - All modules

PAL_45008B symbol

Schematic¶

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.MEM.DATA.PAL_45008_UDATA. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description¶

ND120 PALASM CODE CONVERTED TO VERILOG Component PAL 45008B Last reviewed: 22-MAR-2025 Ronny Hansen

Ports¶

Direction	Width	Name	Description
input	`1`	`CK`	Clock input (added for FPGA synthesis)
input	`1`	`sys_rst_n` (active low)	System reset (active low, for FPGA synthesis)
input	`1`	`MWRITE_n` (active low)	I0 - MWRITE_n
input	`1`	`SWDIS_n` (active low)	I1 - SWDIS_n (SW4 - Parity disable, normal position = down.)
input	`1`	`LBD0`	I2 - LBD0
input	`1`	`LBD1`	I3 - LBD1
input	`1`	`LBD3`	I4 - LBD3
input	`1`	`LBD4`	I5 - LBD4
input	`1`	`BIOXL_n` (active low)	I6 - BIOXL_n
input	`1`	`ECCR`	I7 - ECCR
input	`1`	`BCGNT50R_n` (active low)	I8 - BCGNT50R_n
output	`1`	`DIS_n` (active low)	Y0_n DIS_n (OUT Only)
output	`1`	`OER_n` (active low)	Y1_n OER_n (OUT ONLY)
output	`1`	`OET_n` (active low)	B0_n - OET_n
output	`1`	`CLRERR_n` (active low)	B1_n - CLRERR_n
output	`1`	`DISB_n` (active low)	B2_n - DISB_n (n.c.)
output	`1`	`TST_n` (active low)	B3_n - TST_n (n.c)
input	`1`	`QD_n` (active low)	B4_n - QD_n
input	`1`	`MR_n` (active low)	B5_n - MR_n

Verilog source¶

Verilog/PAL/PAL_45008B.v on GitHub.

Show the Verilog of PAL_45008B (155 lines)

/**********************************************************************************************************
** ND120 PALASM CODE CONVERTED TO VERILOG                                                                **
**                                                                                                       **
** Component PAL 45008B                                                                                  **
**                                                                                                       **
** Last reviewed: 22-MAR-2025                                                                            **
** Ronny Hansen                                                                                          **
***********************************************************************************************************/

// PAL16L8
// ADGD 18/8/86
// 45008B, 2F, DATA

// NOTE: PAL16L8 is purely combinational in the original hardware.
// Clock input added for FPGA synthesis to eliminate latch inference.

// PCB 3202D sheet 46:
//

// PAL 16L8
// 10 INPUT only pins (I0-I9)
// 2 OUT only pins (Y0-Y1) and 6 IN or OUT pins (B0-B5)
//
// PAL16RL8 (https://rocelec.widen.net/view/pdf/c6dwcslffz/VANTS00080-1.pdf)


module PAL_45008B (
    input CK,         //! Clock input (added for FPGA synthesis)
    input sys_rst_n,  //! System reset (active low, for FPGA synthesis)

    input MWRITE_n,   //! I0 - MWRITE_n
    input SWDIS_n,    //! I1 - SWDIS_n (SW4 - Parity disable, normal position = down.)
    input LBD0,       //! I2 - LBD0
    input LBD1,       //! I3 - LBD1
    input LBD3,       //! I4 - LBD3
    input LBD4,       //! I5 - LBD4
    input BIOXL_n,    //! I6 - BIOXL_n
    input ECCR,       //! I7 - ECCR
    input BCGNT50R_n, //! I8 - BCGNT50R_n
    // input HIEN_n,  //! I9 - EPEA_n  (NOT USED!)


    output DIS_n,  //! Y0_n DIS_n (OUT Only)
    output OER_n,  //! Y1_n OER_n (OUT ONLY)

    output OET_n,     //! B0_n - OET_n
    output CLRERR_n,  //! B1_n - CLRERR_n
    output DISB_n,    //! B2_n - DISB_n (n.c.)
    output TST_n,     //! B3_n - TST_n (n.c)
    input  QD_n,      //! B4_n - QD_n
    input  MR_n       //! B5_n - MR_n
);


  // Creating non-negated wires for active-low inputs
  wire MWRITE = ~MWRITE_n;
  wire SWDIS = ~SWDIS_n;
  //wire LBD0_n = ~LBD0;
  //wire LBD1_n = ~LBD1;
  //wire LBD3_n = ~LBD3;
  //wire LBD4_n = ~LBD4;
  wire BIOXL = ~BIOXL_n;
  wire ECCR_n = ~ECCR;
  wire BCGNT50R = ~BCGNT50R_n;
  //wire HIEN = ~HIEN_n;
  wire QD = ~QD_n;
  wire MR = ~MR_n;


  // Register and wire declarations (moved before assign to avoid synthesis warning)
  reg  DISB_reg;
  reg  TST_reg;
  wire TST = TST_reg;
  wire DISB = DISB_reg;

  // ON WRITE TO MEMORY
  assign OET_n = ~(MWRITE);

  // ON READ FROM MEMORY AFTER THE ADDRESS PE
  // ON WRITE IN TEST MODE BOTH OER AND OET S
  assign OER_n = ~((BCGNT50R) | (TST & MWRITE));


  // CLEAR PARITY ERROR ON MR, READING EPESL
  assign CLRERR_n = ~(MR | BCGNT50R_n | DISB | QD);


  // DIS logic
  assign DIS_n = ~(DISB | SWDIS);


`ifdef USE_TRANSPARENT_LATCHES
  // Transparent latch (original behavior for simulation)
  /* verilator lint_off LATCH */
  always @(*) begin
    if ((LBD3 & BIOXL & ECCR) == 1) DISB_reg = 1'b1;
    // PALASM 45008B: hold = /MR*DISB*/BIOXL + /MR*DISB*/ECCR - clear ONLY
    // when ALL hold terms fail: MR or the NEXT IOX addressed to ECCR
    // (30-JUL audit: was OR of the negated hold terms, dropping DISB on any
    // IOX anywhere).
    else if (MR | (BIOXL & ECCR))
      DISB_reg = 1'b0;

    if (((LBD0 & BIOXL & ECCR) == 1) | ((LBD1 & BIOXL & ECCR) == 1) | ((LBD4 & BIOXL & ECCR) == 1))
      TST_reg = 1'b1;
    // PALASM 45008B: hold = /MR*TST*/BIOXL + /MR*TST*/ECCR - same clear rule
    // as DISB (30-JUL audit: OR-for-AND plus BIOXL where /BIOXL belongs).
    else if (MR | (BIOXL & ECCR))
      TST_reg = 1'b0;
  end
  /* verilator lint_on LATCH */
`else
  // Edge-triggered flip-flop (FPGA synthesis)
  always @(posedge CK or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
      DISB_reg <= 1'b0;
      TST_reg <= 1'b0;
    end else begin
      if ((LBD3 & BIOXL & ECCR) == 1) DISB_reg <= 1'b1;
      // Clear rule per PALASM (see latch branch comment, 30-JUL audit fix)
      else if (MR | (BIOXL & ECCR))
        DISB_reg <= 1'b0;

      if (((LBD0 & BIOXL & ECCR) == 1) | ((LBD1 & BIOXL & ECCR) == 1) | ((LBD4 & BIOXL & ECCR) == 1))
        TST_reg <= 1'b1;
      // Clear rule per PALASM (see latch branch comment, 30-JUL audit fix)
      else if (MR | (BIOXL & ECCR))
        TST_reg <= 1'b0;
    end
  end
`endif


  assign DISB_n = ~DISB_reg;
  assign TST_n  = ~TST_reg;

endmodule



/*


DESCRIPTION

; 200387 CJTC: LOGICAL ERRORS IN EQUATIONS FOR DISB AND TST
; 260387 CJTC: CHANGED PIN 2 /EPESL TO /EPEAL - CIRCUIT CHANGE ONLY!!!
; 260387 JLB: CLRERR COMES IMMEDIATELY TO MAKE PERR0&1 PULSES ONLY!!!

; 180587 M3202B
; 091087 B CJTC: AM29833 ARE GIVING ERROR OUTPUT EVEN BEFORE CLOCKED.
;                QD GOES INACTIVE ON 6, JUST BEFORE RDATA THUS STOPPING
;

*/