PAL_44310D¶

Source: Verilog/PAL/PAL_44310D.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > MEM_43 > MEM_LBDIF_48 > PAL_44310D - instance path: CORE.CPU_BOARD.MEM.LBDIF.PAL_44310_ULBDIF

Used in: MEM_LBDIF_48 (all tops)

Contains: no other modules.

Module hierarchy - All modules

PAL_44310D symbol

Schematic¶

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.MEM.LBDIF.PAL_44310_ULBDIF. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

Description¶

ND120 PALASM CODE CONVERTED TO VERILOG Component PAL 44310D Last reviewed: 2-FEB-2025 Ronny Hansen

Ports¶

Direction	Width	Name	Description
input	`1`	`CK`	Clock input (added for FPGA synthesis)
input	`1`	`sys_rst_n` (active low)	System reset (active low, for FPGA synthesis)
input	`1`	`HIEN_n` (active low)	I0
input	`1`	`BGNT_n` (active low)	I1
input	`1`	`CGNT_n` (active low)	I2
input	`1`	`LOEN_n` (active low)	I3
input	`1`	`CGNT50_n` (active low)	I4
input	`1`	`ECCR`	I5
input	`1`	`BGNT50_n` (active low)	I6
input	`1`	`BGNT75_n` (active low)	I7
input	`1`	`BDAP50_n` (active low)	I8
input	`1`	`MR_n` (active low)	I9
output	`1`	`BDRY_n` (active low)	B0
output	`1`	`BIOXL_n` (active low)	B1
input	`1`	`RAS`	B2
input	`1`	`REF100_n` (active low)	B3
input	`1`	`BIOXE_n` (active low)	B4
input	`1`	`MWRITE50_n` (active low)	B5
output	`1`	`BCGNT50R_n` (active low)	Y0
output	`1`	`RDATA`	Y1

Verilog source¶

Verilog/PAL/PAL_44310D.v on GitHub.

Show the Verilog of PAL_44310D (141 lines)

/**********************************************************************************************************
** ND120 PALASM CODE CONVERTED TO VERILOG                                                                **
**                                                                                                       **
** Component PAL 44310D                                                                                  **
**                                                                                                       **
** Last reviewed: 2-FEB-2025                                                                             **
** Ronny Hansen                                                                                          **
***********************************************************************************************************/



//PAL16L8
//ADGD 13/8/86
//44310D,3F,LBDIF

// NOTE: PAL16L8 is purely combinational in the original hardware.
// Clock input added for FPGA synthesis to eliminate latch inference.

module PAL_44310D (
    input  CK,        //! Clock input (added for FPGA synthesis)
    input  sys_rst_n, //! System reset (active low, for FPGA synthesis)

    input  HIEN_n,    //! I0
    input  BGNT_n,    //! I1
    input  CGNT_n,    //! I2
    input  LOEN_n,    //! I3
    input  CGNT50_n,  //! I4
    input  ECCR,      //! I5
    input  BGNT50_n,  //! I6
    input  BGNT75_n,  //! I7
    input  BDAP50_n,  //! I8
    input  MR_n,      //! I9

    output BDRY_n,     //! B0
    output BIOXL_n,    //! B1
    input  RAS,        //! B2
    input  REF100_n,   //! B3
    input  BIOXE_n,    //! B4
    input  MWRITE50_n, //! B5

    output BCGNT50R_n, //! Y0
    output RDATA       //! Y1
);


  // Creating non-negated wires for active-low inputs
  wire HIEN = ~HIEN_n;
  wire BGNT = ~BGNT_n;
  wire CGNT = ~CGNT_n;
  wire LOEN = ~LOEN_n;
  wire BGNT50 = ~BGNT50_n;
  wire BGNT75 = ~BGNT75_n;
  wire BDAP50 = ~BDAP50_n;
  wire MWRITE50 = ~MWRITE50_n;
  wire BIOXE = ~BIOXE_n;

  wire BIOXL = ~BIOXL_n;
  wire CGNT50 = ~CGNT50_n;
  wire REF100 = ~REF100_n;

  wire RAS_n = ~RAS;


  // Logic for BCGNT50R_n (active-low)
  assign BCGNT50R_n = ~((MWRITE50_n & BGNT & BGNT50) |  // FROM 50NS AFTER GNT ON READ C
      (MWRITE50_n & CGNT & CGNT50)  // LASTS FOR THE REST OF THE CYCLE
      );

  // Logic for BDRY_n (active-low)
  reg BDRY;

`ifdef USE_TRANSPARENT_LATCHES
  // Transparent latch (original behavior for simulation)
  /* verilator lint_off LATCH */
  always @(*) begin
    if ((MWRITE50_n & BDAP50 & BGNT & LOEN_n & HIEN_n & RAS_n) |  // BUS READ FROM LOCAL MEM
        (MWRITE50 & BDAP50 & BGNT50 & BGNT) |  // BUS WRITE TO LOCAL MEM
        (BIOXL & ECCR) |  // IOX=ECCR
        (REF100) | (MWRITE50_n & BDAP50 & BGNT50_n & BGNT75)  // LATE BDRY FOR 10MHZ DISK
        )
      BDRY = 1'b1;
    // PALASM 44310D: hold = /MR*BDRY*BDAP50 + /MR*BDRY*BIOXE - BDRY holds
    // while MR_n & (BDAP50 | BIOXE); clear only when BOTH hold terms fail
    // (30-JUL audit: was OR of the negated terms, so the memory hold never
    // held in DMA cycles where BIOXE is off - lost/shortened BDRY, the exact
    // failure this PAL's own 1986 errata describes).
    else if (~MR_n | (~BDAP50 & ~BIOXE))
      BDRY = 1'b0;
  end
  /* verilator lint_on LATCH */
`else
  // Edge-triggered flip-flop (FPGA synthesis)
  always @(posedge CK or negedge sys_rst_n) begin
    if (!sys_rst_n) begin
      BDRY <= 1'b0;
    end else begin
      if ((MWRITE50_n & BDAP50 & BGNT & LOEN_n & HIEN_n & RAS_n) |
          (MWRITE50 & BDAP50 & BGNT50 & BGNT) |
          (BIOXL & ECCR) |
          (REF100) | (MWRITE50_n & BDAP50 & BGNT50_n & BGNT75))
        BDRY <= 1'b1;
      // Clear rule per PALASM (see latch branch comment, 30-JUL audit fix)
      else if (~MR_n | (~BDAP50 & ~BIOXE))
        BDRY <= 1'b0;
    end
  end
`endif

  assign BDRY_n = ~BDRY;

  // Logic for BIOXL_n (active-low)
  assign BIOXL_n = ~(BIOXE & BGNT_n & CGNT_n);

  // Logic for RDATA
  assign RDATA = ~((MWRITE50) |  // INDICATES DATA READY ON
      (LOEN) | (HIEN) | (BGNT_n & CGNT_n) | (RAS));

endmodule

/*

DESCRIPTION

:280287 JLB: ECCR WRONG POLARITY, RESPONDS WITH BDRY TO
;EXISTING IOX-ES.
;280287 JLB: NEW INPUT REF~ , TO GENERATE A REF PULSE OF 175-200NS
;DURATION BY GENERATING BDRY.
;
;180587 M3202B
;090787 B JLB: RAS USED IN RDATA TO AVOID SPIKE ON TRANSITION FROM
;              LOEN TO HIEN.
;290787 C JLB: BD HAD A TYPICAL SETUP TIME OF 140NS BEFORE BDRY ON DMA READ
;              CHANGED TO 65NS (25NS REQUIRED). DMA BUFFERED WRITE: BDRY START
;              50NS AFTER BGNT GOES ACTIVE ON DMA WRITE, AND LASTS UNTIL BGNT
;              OR BDAP50 GOES OFF (105NS MIN.}. THIS IS TO GIVE TIME FROM
;              GRANT OFF TO BMEM ON IN THE FOLLOWING CYCLE.
;110887 D JLB: BDRY GAN BE LOST IF BDRY50 IS NOT PRESENT AT THE TIME STATE
;              7 IN THE RAM CONTROL IS REACHED. HAPPENS WITH 1OMHZ DISK CONTR.
;              SINTRAN STOPS ON LEVEL 14 DURING STARTUP.

*/