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F091

Source: Verilog/DECODE-GateArray/DGA/circuit/F091.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > IO_37 > IO_DCD_38 > DECODE_DGA > F091 - instance path: CORE.CPU_BOARD.IO.DCD.DGA.A090

Used in: DECODE_DGA (all tops), DECODE_DGA_COMM (all tops), DECODE_DGA_IDBS (all tops), DECODE_DGA_POW (all tops)

Contains: no other modules.

Module hierarchy - All modules

F091 symbol

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.IO.DCD.DGA.A090. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

F091 schematic

Description

ND120 DGA (Decode Gate Array) DECODE/DGA NEC F091 - H,L LEVEL GENERATOR Last reviewed: 20-MAY-2024 Ronny Hansen

Ports

Direction Width Name Description
output 1 N01
output 1 N02

Verilog source

Verilog/DECODE-GateArray/DGA/circuit/F091.v on GitHub.

Show the Verilog of F091 (17 lines) 
/**************************************************************************
** ND120 DGA (Decode Gate Array)                                         **
** DECODE/DGA                                                            **
**                                                                       **
** NEC F091 -  H,L LEVEL GENERATOR                                       **
**                                                                       **
** Last reviewed: 20-MAY-2024                                            **
** Ronny Hansen                                                          **
***************************************************************************/
module F091 (
    output N01,
    output N02
);
  assign N01 = 1'b1;  // High
  assign N02 = 1'b0;  // Low

endmodule