Skip to content

F103

Source: Verilog/DECODE-GateArray/DGA/circuit/F103.v

Where it sits (Simulation): ND120_TOP > ND120_CORE > ND3202D > IO_37 > IO_DCD_38 > DECODE_DGA > DECODE_DGA_POW > F103 - instance path: CORE.CPU_BOARD.IO.DCD.DGA.POW.A628

Used in: DECODE_DGA_POW (all tops)

Contains: no other modules.

Module hierarchy - All modules

F103 symbol

Schematic

Drawn from the Verilog: the yosys netlist of the Simulation (Verilator) build, instance CORE.CPU_BOARD.IO.DCD.DGA.POW.A628. Sub-modules are boxes (click the picture to open it full size; there every sub-module box links to its page, and every wire shows its Verilog name).

F103 schematic

Description

ND120 DGA (Decode Gate Array) DECODE/DGA NEC F103 - Inverter x3 signal drive Last reviewed: 20-MAY-2024 Ronny Hansen

Ports

Direction Width Name Description
input 1 F_IN
output 1 F_OUT

Verilog source

Verilog/DECODE-GateArray/DGA/circuit/F103.v on GitHub.

Show the Verilog of F103 (18 lines) 
/**************************************************************************
** ND120 DGA (Decode Gate Array)                                         **
** DECODE/DGA                                                            **
**                                                                       **
** NEC F103 - Inverter x3 signal drive                                   **
**                                                                       **
** Last reviewed: 20-MAY-2024                                            **
** Ronny Hansen                                                          **
***************************************************************************/

module F103 (
    input  F_IN,
    output F_OUT
);

  assign F_OUT = ~F_IN;

endmodule