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BIG MULTIPORT MEMORY SYSTEM

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REVISION RECORD

Revision	Notes
Aug. 1978	Original Printing

BIG MULTIPORT MEMORY SYSTEM
ND-06.007.01

NORSK DATA A.S.
Lørenveien 57, Postboks 163 Økern, Oslo 5, Norway

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TABLE OF CONTENTS

Section:	Page:
1	BIG MULTIPORT MEMORY SYSTEM
1.1	General
1.2	The Memory System
1.3	System Parts
1.3.1	Crate
1.3.2	Bank
1.3.3	Controller (1144)
1.3.4	Storage (1132's)
1.3.5	Port (1142, 1143)
1.3.6	Channel
1.3.7	Source
1.3.8	Service Channel
1.4	Addressing
1.4.1	Address Conversion
1.4.2	Bank Selection
1.4.3	Interleave (Shifted Address)
1.5	Data
1.5.1	Format
1.5.2	Data Protection
1.5.2.1	General about Error Detection and Correction
1.5.2.2	Write
1.5.2.3	Read
1.5.2.4	Single Data Error
1.5.2.5	Single Control Code Error
1.5.2.6	Multiple Error
1.5.3	Control and Error Reporting
2	MEMORY CHANNEL SPECIFICATIONS
2.1	Hardware Specifications
2.1.1	Signal Standard
2.1.2	Cable
2.1.3	Connector
2.1.4	Termination
2.2	Signal Description
2.2.1	Address Cable Signals
2.2.2	Data Cable Signals
2.3	Channel Timing
2.3.1	Address and Cycle Times
2.3.2	Latency
2.3.3	Timeout
2.4	32 Bits Channel
2.5	Indicators
2.6	Address Range Switch
2.7	Disable Error Correction Switch

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Section

| Page: |

3 SERVICE CHANNEL SPECIFICATIONS | 3-1

3.1 General | 3-1

3.1.1 Error Log (1145) | 3-1

3.2.1 Error Log I/O Interface | 3-2

3.2 Programming Specifications | 3-2

3.1.2 Device Number | 3-2

3.2.2 Interrupt Level = 13₁₀ | 3-2

3.2.3 Ident Code = 5 | 3-2

3.2.4 Load Command Register = IOX 751 | 3-3

3.2.5 Read Scan Register = IOX 750 | 3-4

3.2.6 Read Status Register = IOX 752 | 3-5

3.2.7 Load Control Register = IOX 753 | 3-6

3.3 Detailed Description of Commands | 3-6

3.3.1 Action 00: Initiate Scan of Error Log | 3-7

3.3.2 Action 01: Initiate Scan of Port Status | 3-8

3.3.3 Action 10: Load Error Correction Control Register, ECC | 3-9

3.3.3.1 Test Error Correction | 3-10

3.3.4 Action 11: Execute Test Accesses | 3-10

3.3.4.1 Address and Data of Test Accesses | 3-11

3.4 Hardware Specifications | 3-11

3.4.1 Electrical Standard | 3-11

3.4.1.1 Termination | 3-12

3.4.2 Service Channel Signals | 3-12

3.4.3 Channel Timing | 3-12

3.4.4 Error Indicator | 3-12

3.4.5 Crate Number Switch | 3-13

4 CONTROL CHANNEL SPECIFICATIONS | 4-1

4.1 Functional Description | 4-1

4.1.1 Memory Inhibit/Power Fail | 4-1

4.1.2 Refresh Synchronization | 4-1

4.2 Electrical Specifications | 4-1

4.3 Channel Signals | 4-2

5 INSTALLATION | 5-1

5.1 Switch Setting | 5-1

5.1.1 Address Range Selection | 5-1

5.1.2 Crate Number Setting | 5-2

5.1.3 Manual Disabling of Error Correction | 5-3

5.2 Control Channel Connection | 5-3

5.2.1 Memory Inhibit | 5-3

5.2.2 Refresh Synchronization | 5-3

5.3 Channel Expansion | 5-5

5.3.1 Daisy Chaining | 5-5

5.3.2 Termination | 5-6

5.4 Configuration Structure | 5-6

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Appendix

Appendix	Page
A	BMPM TO MPM COMPARISON
B	CONVERSION CHARTS
B.1	Conversion between Logical Code and Physical Position of Faulty IC's on 1132 Module
B.2	Conversion between Logical Code and Physical Slot of Faulty Storage Modules
B.3	Physical Position of Range Limit Switches Indicated by the Bank/Port Code
C	CABLE AND WIRING LISTS
D	LOGIC DIAGRAMS
E	RS-422 STANDARDS
E.1	Summary of EIA RS-422 Standard for a Balanced Differential Interface
E.2	EIA Standard RS-422
F	CONTENT OF DEFINED ND NUMBERS

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List of Illustrations

Figure

Figure	Description	Page
1.1	Multiport Configuration — Example	1-3
1.2	Multiport Memory (1 card crate)	1-4
1.3	Use of Internal Bank Address	1-6
1.4	Channel Signals	1-8
1.5	Scan Error Log	1-9
1.6	Scan Port Status	1-10
1.7	Write ECC Register	1-11
1.8	Execute Test Access	1-12
1.9	Bank Selection / Channel to Bank Address Conversion	1-14
1.10	Storage to Port Communication	1-15
1.11	Shifting of Address Bits	1-16
1.12	The Banks as Seen from NORD-10/S	1-17
1.13	The Banks as Seen from NORD-50	1-17
1.14	Channel Data Format	1-18
1.15	Syndrome Decoding	1-20
1.16	Data Flow on Write	1-21
1.17	Reading Data (No Error)	1-22
1.18	Reading Data (Single Error)	1-23
1.19	Reading Data (Multiple Error)	1-23
1.20	I/O Interrupt System in NORD-10/S	1-25
1.21	Big MPM Data (1143) — Data Flow	1-26
2.1	Termination of Memory Channel Signals	2-2
2.2	Memory Channel Timing Specifications Measured at Port Terminals	2-4
2.3A	Memory Channel Write Access Timing	2-5
2.3B	Memory Channel Read Access Timing	2-5
2.4	Two 16 Bits Banks Accessed as One 32 Bit Bank	2-7
3.1	BMPM Service Channel	3-13
3.2	I/O Module to Error Log Module Communication	3-14
3.3	Scan of Error Log — Block Diagram	3-15
3.4	Action: 00 Scan of Error Log — Flow Diagram	3-16
3.5	Beginning and Continuation of a Scan (termination is shown in Figure 3.10)	3-17
3.6	Scan of Port Status — Block Diagram	3-18
3.7	Action: 01 Scan of Port Status — Flow Diagram	3-19
3.8	Execution of Actions 10 or 11	3-20
3.9	Execution of Actions 00 or 01	3-20
3.10	Termination of a Scan (diagram continues from Figure 3.5)	3-21
3.11	Error Log Module Port Communication	3-22
3.12	Service Channel Timing Specifications according to Figure 3.1 - 3.4	3-23
3.13	Start/Stop of Scan (no error found)	3-24
3.14	Scan Hit	3-25
4.1	Electrical Specifications	4-2
5.1	Limit Switches	5-1
5.2	Limit Switch Setting	5-2
5.3	Indicators	5-3
5.4	Memory Inhibits Connections in Backwiring	5-4
5.5	Refresh Synchronization at Control Modules in Slot 9 or 28	5-4
5.6	Three Modes of Refresh Operation for a Bank	5-5
5.7	Internally Connected Plug Fields Used for Channel Expansion	5-5

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Figures and Pages

Figure	Description	Page
C.1	Memory Channel — Address	C-2
C.2	Memory Channel — Data	C-3
C.3	Service Channel	C-4
C.4	Control Channel	C-5
C.5	Wire Wrapping on ND-146	C-6
C.6	Terminator Plugs	C-7
C.7	Memory Channel — Address Interleave Cable	C-8

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BIG MULTIPORT MEMORY SYSTEM

1.1 GENERAL

The Big Multiport Memory System (referred to as BMPM) is a high speed flexible and modular memory system used for two major applications:

1. Increased memory band width to enable for higher total data transfer rates to and from memory.
2. Allow for multiprocessor and/or multi-device communication via a common memory system.

This is accomplished by using a number of independent memory banks accessed by a number of independent memory ports. The system is modular with respect to banks, channels and storage capacity.

Each memory channel has an address range of 2048K words and may be connected from 1 to 10 ports.

Single bit error correction and multiple error detection is standard.

A special service channel is provided for a number of operations and maintenance purposes.

1.2 THE MEMORY SYSTEM

A memory system (refer to Figure 1.1) is a collection of independent banks, each covering a definite address space. Every bank is linked together and to the outside world by Channels. The entrance for channels is called Ports. The Channels in the system are driven from Sources.

The Sources are interfaces between the memory system and the unit demanding access. In order to maintain a well-defined intersection the sources are not considered part of the memory system.

In addition to the ordinary channels a special service channel exists. All banks are linked to the service channel which is driven from an I/O interface.

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1.3 SYSTEM PARTS

1.3.1 Crate

For the following discussion refer to Figure 1.2.

Although the bank is logically the basic building block, the card rate is physically the basic unit, containing one or two banks, an X-bank and a Y-bank. This is done purely for space and wiring reasons. In BMPM there is no logic in common between the two banks as it is on the former model. Yet the service channel has common logic since it will always be connected in a predetermined manner.

A maximum of 8 crates can be used in a Memory system.

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Figure 1: Multiport Configuration — Example

Sources

Source I
NOR-D-10/S

Source II
NOR-D-50

Source III
NOR-D-10

Source IV
DISK

Channels

• 16 bits CPU Channel
• 32 bits CPU Channel
• 16 bits DMA Channel
• Service Channel

Banks

Bank X0
A
B
C
D

Bank Y0
A
B
C
D

Bank Y1
A
B
C
D

Modules

Code
1211, 1213
1500, 1501, 1519
1068, 1079
1083, 1096

Error Log / I/O Interface
I/O card crate

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Multiport Memory (1 card crate)

X-Bank

Storage

• X-Bank Modules
  • 32-256

• Control Bank X

Port Address

• Port Address
  • A, B, C, D
  • 0, 1, 2, 3, 4, 5, 6, 7
    • 39
    • 19

Port Data A

• X/Y Log
  • Expansion

Y-Bank

Storage

• Y-Bank Modules
  • 32-256

• Control Bank Y

Port Address

• Port Address
  • A, B, C, D
  • 0, 1, 2, 3, 4, 5, 6, 7
    • 39
    • 19

Port Data A

• X/Y Log
  • Expansion

Expansion

• 32K RAM (1432)

Big NPH Modules

• Big NPH Control (1144)
• Big NPH Address (1442)
• Big NPH Data (1443)

Error Log

• Big NPH Error Log (1145)

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The Error Log Module may go in POS 18 or 19.

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Switch determines X/Y bank module. Details in system card crate number 071. The maximum cards in a system is 8.

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1.3.2 Bank

A bank is an independent memory unit that can cycle by itself. It also has its own timing and control logic.

Two banks can be located in one card crate, one X-bank and one Y-bank.

A complete bank consists of the following parts:

• Controller (1144)
• Storage (1132's)
• Ports (1142, 1143)
• Error logic (1145)

1.3.3 Controller (1144)

It is essential that a bank has a private controller which allows it to operate independent of other banks.

The controller solves two major tasks.

1. To serve as a "switchboard" between the ports on one side and the storage on the other

2. To refresh the MOS memory elements at regular intervals.

Since up to 4 ports (A - D) may access the same storage, a priority network allocates the storage to one port for one storage cycle at a time.

The ports and refresh are assigned a fixed priority which is, beginning at the highest priority:

Priority Order	Description
1	New request from same port as previous one
2	REFRESH
3	PORT A
4	PORT B
5	PORT C
6	PORT D

When two ports make requests simultaneously, the highest priority port will be served first.

Note: It is not possible for one high priority port to lock out the lower priority ones. The reason is that the request must toggle on and off.

Even if a channel is capable of absorbing everything it could get from memory, it must withdraw the request for a moment to prepare for the next. At that very moment, the lower-priority port will be granted access.

However, two high priority ports are able to lock the bank for lower priority ports.

Periodic refresh is necessary in MOS memories to avoid decline of information. This is accomplished by regularly accessing all memory cells. These accesses (one each 15 µs) may be treated similar to accesses from the ports.

The refresh request circuitry and refresh address counter is located in the controller (1144).

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1.3.4 Storage (1132's)

An X-bank has room for 8 storage modules and a Y-bank has room for 4 storage modules. Each module contains 32K x 21 memory cells (bits). Hence, one X-bank is sufficient to cover all NORD-10/S’ primary storage requirements of 256K words.

Internally in the bank the address range is always from 0 in 32K increments up to 256K. Hence, an address transformation is normally required at each port. (Refer to Section 1.4 regarding addressing.)

The 18 address bits required for a 256K address range are used as shown in Figure 1.3.

The memory integrated circuits (MIC) contain 16K x 1 bit. Hence, two MIC’s are needed per data bit on a 32K module. Since storage of 21 data bits are required each storage module contains 42 MIC’s. The 5 extra bits are used by the control code attached to the 16 data bits. (Error checking and correction is described in Section 1.5.)

17------15	14	--------------------------------------	1
Select module	Select one of 16384 cells in MIC	Select odd or even MIC

Figure 1.3: Use of Internal Bank Address

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1.3.5 Port (1142, 1143)

A port is the entrance for a channel to a bank. A bank holds from 1 to 4 ports (A - D). A port consists of receivers for addresses and transmitters and receivers for data and control lines.

Up to 10 ports can be linked together (daisy chained) by a channel, i.e., a source can access up to 10 banks of storage.

A port consists of a data (1143) and an address (1142) module. A port carries out two major functions:

1. Select a bank for the source and convert the channel address to a local bank address (1142).

2. • Generate a 5 bit control code to be attached to data during write
   • Check the data against the control code during read.

Each port defines the address range for a bank (1142). (Refer to Section 1.4.) Normally, the address range is the same as seen from the different ports, but for special purposes they will be different. One such example is the NORD-10/NORD-50 communication using BMPM as a common memory.

1.3.6 Channel

In the memory system a Channel is physically a pair of cables. One cable carries address and request signals while the other carries data and ready signals. With the word channel we will normally mean a 16 bit data channel. It is, however, possible to define a 32 bit channel consisting of one address cable and two data cables. Since all ports are 16 bits wide, two ports are required in that case. A 32 bits channel is illustrated in Figure 1.1.

All channels meet only one type of port. Hence, all sources must conform to the same specifications when requesting memory.

It is normally possible to connect several banks to one channel.

Every port has one input and one output connector for each cable, which allows daisy chaining of up to 10 ports. At the end of the chain a termination plug is mounted.

Note: The two banks in the same crate have their ports daisy chained internally. Figure 1.4 shows signals appearing on a channel.

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CHANNEL

Source		Port
Request	1	(REQL)
Address	21	BA 0L- BA 21L
Direction	1	WRITEL
Address ready	1	ARL
Data ready	1	DRL
Data	18	BO 0L- BO 17L

Figure 1.4: Channel Signals

Note 1: A 32 bits channel consists of one address cable and two data cables.

Note 2: Up to 10 ports may be chained to one source. The cables must be terminated in the last port.

Note 3: Transmitters and receivers in the ports meet the RS-422 specifications. (Refer to Appendix E.)

1.3.7 Source

A Source can be any kind of electronic unit which is capable of communicating with BMPM over a channel. Examples of sources can be: NORD-10, NORD-10/S, NORD-50 or DMA interfaces. The sources must conform to the channel specifications (refer also to Figure 1.1).

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1.3.8 Service Channel

The service channel consists of an error log module (1145) located in the BMPM, an error log I/O interface module (1146) located in the NORD-10/S input/output system and a cable connecting those two modules together. BMPM will thus be regarded as an I/O device as seen from NORD-10/S.

The error log module (1145) is logically divided into two parts, one serves the X-bank and the other the Y-bank. Each part contains an error log memory. All errors (single or multiple) occurring in the bank and detected by the ports (1143's), will be recorded in this special memory. The error log memory is organized as a 512 x 1 bit memory where the address is a pointer to the failing memory integrated circuit (MIC).

A thumb wheel switch located on this module defines the crate number (0 - 7).

The service channel can perform the following four functions:

1. (Action: 00), Refer to Figure 1.5.

   Scan the error log memory for a failing bit. The error log memory address where the failing bit is found (pointer to the failing MIC) is transferred to a one-word scan register located in the error log I/O interface (1146).

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1145
Error Log
Memory
Address
containing
a "one" bit
(Data Error)

CPU
A Register

1146
Scan Register

Figure 1.5: Scan Error Log

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1–10

2. (Action: 01), Refer to Figure 1.6.

Scan the present ports for bank address range setting. This operation will also give the information whether the ports have detected an error or not.

Steps 1 and 2 are feedback information from the BMPM and will be written into the scan register located in the error log I/O interface (1146). This will be transferred to the A register of the CPU by execution of an IOX <Read Scan Register> (IOX 750).

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| PORT A    | PORT B | etc.                   |
|-----------|--------|------------------------|
| UL        |        | Port Switch Setting    |
| (Upper    |        | and Error Report       |
| Limit)    |        |                        |
| LL        |        |                        |
| (Lower    |        | Error reported from    |
| Limit)    |        | scanned port           |

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| CPU        | 1146         |
|------------|--------------|
| A Register | Scan Register|
|            | IOX          |
|            | `<Read Scan  |
|            | Register>`   |

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Figure 1.6: Scan Port Status

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1–11

1. (Action: 10), Refer to Figure 1.7.

   Set the content of the error correction control register (ECC) located in the data module (1143) of the ports.

2. (Action: 11), Refer to Figure 1.8.

   Execute test access. A read or write operation can be simulated without a channel connected.

Steps 3 and 4 are control information for the BPMM. The control information is transferred from the A register in the CPU to the command register located in the error log I/O interface (1146) by executing an IOX <Load Command Register> (IOX 751). From this register the control information is sent to BPMM via the error log module (1145).

Information regarding detailed description of programming specifications and word formats is given in Chapter 3.

![Figure 1.7: Write ECC Register]

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Component	Description
ECC	Control information to ECC (Error Correction Control)
CPU	A Register
IOX <Load Command Register>	Command executed

Figure 1.7: Write ECC Register

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Execute Test Access

          |                     | 1145
          | . . . . . . . . . .|
          | Port B             |
          | Port A             |
          | . . . . . . . . . .| Read or Write
                               | Test access request
          | . . . . . . . . . .| 
          |  CPU               | 1146
          | |--------------|   | . . . . . . . . . .
          | | A register   |   | 
          | |--------------|   | 
          | . . . . . . . . . .|
             IOX <Load Command Register >

Figure 1.8: Execute Test Access

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1.4 ADDRESSING

1.4.1 Address Conversion

The total address range of a channel is 2048K (21 address bits). Since each bank has a range of 256K, 8 banks are necessary to cover the complete range. Hence, the 3 most significant address bits could be decoded for bank selection.

However, since the minimum size of a bank is 32K (1 storage module) it is desirable that one has a resolution of 32K for selection. Hence, the 6 most significant bits are needed for decoding of 32K banks.

Straight decoding requires banks of equal size, so to permit banks of different sizes a more flexible method is required.

Each port has therefore a set of limit switches which define the address range the port will respond to.

One pair determines lower limit, LL, and one pair determines upper limit, UL. Each pair holds a two-digit octal number. Refer to the chart in Figure 1.9 for the corresponding address range.

When a request appears on the channel, all ports test the address against their limit switches. The request shall have access if:

LL ≤ Channel Address < UL

Inside all banks the address range is 0 - 256K, so the channel address must normally be transformed to an internal bank address which is offset by the lower limit (LL).

This transformation is performed at the port, and it is a simple subtraction:

Bank Address = Channel Address − Lower Limit

Accordingly, channel address equal to lower limit is directed into bank address 0.

Observe that two channels may access the same memory cell although their channel addresses are different. Address skew between channels should be avoided as much as possible since it makes the system very opaque both from a hardware and software point of view.

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Bank Selection/Channel to B-Address Conversion

Figure 1.9

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Diagram Components

• Source 2, Source C, Source G
  • Inputs connected to REL (Priority Encoder).

• Port A, Port B, Port C, Port D
  • Maximum 4 per bunk.
  • Connected to DMA Channel Interface.

• Priority
  • Allocates bus priority and manages DMA channel requests.

• Channel Address (CH. 0-20)
  • Bank address for storage selection.

• Storage
  • 32-256 K capacity per bank.

• Maximum Configuration
  • Max no. of card crates: 8
  • Max no. of ports/crate: 8
  • Max no. of ports/board: 64
  • Max no. of ports on one channel: 64

Address Management

• Upper (MOVR) and Lower (LDR) Unit Switch Settings:
  • Each switch setting corresponds to different address ranges.

Settings	Response
00	4 k
01	8 k
10	16 k
11	32 k

• Address range subdivided into page 0 to page 3 with relays for channel communication.

Notes

• TERMINATION on the last port requires a special setting.
• CHML represents the channel multiplexer.

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1.4.2 Bank Selection

For the following discussion refer to Figure 1.9.

When a source places an address on the bus together with a Request all the ports linked together by the channel will examine the channel address. The port (1142) that finds the channel address within its limits (LL ≤ A < UL) will forward the request to the controller (1144).

Since the 4 ports associated with a given bank operate completely asynchronously with respect to each other, a priority network is required. The highest priority port will then be allocated to storage for one memory cycle. The bank address = (channel address – lower limit) will then be enabled onto the local bank address bus.

For further information regarding storage to port communication refer to Figure 1.10.

Ports 1142/1143	Storage 1132
A	Request
B	1 (BREQ)
C	Direction
D	1 (BW/RTE)
	Not used / Reset data Enable
	1 BRDATA
	Data
	22 BD 0-21
	Reset address
	1 BAR
	Data ready
	1 BDR
	Bank Expansion Address
	2 BA 18-19
	Bank Address
	18 BA 0-17
	Not used / BA 1-7
Control 1144	Refresh address (row address)
	7
	Storage busy
	1 BMBUSY
	Start refresh
	1 BREFRESH

Figure 1.10: Storage to Port Communication

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1.4.3 Interleave (Shifted Address)

To increase memory band width an interleave technique can be used. However, it is only meaningful in a pipeline system where a new request is issued before the previous is serviced.

In a less critical sense "interleave" is used to designate shifting of the address bits.

If the address is rotationally shifted one place to the right, bit 0 will receive position 20, bit 20 position 19 and so on. The effect is that all even addresses will seem to lie between 0 and 1024K while all odd addresses will appear as lying between 1024K and 2048K.

Two consecutive addresses (as seen from program) will therefore lie in different banks. The band width benefit expectation from this shifting is greatly exaggerated when memory accesses are not pipelined.

However, interleaving is necessary when 16 bit and 32 bit channels are to communicate.

Two 16 bit words, at consecutive addresses, may be read as one 32 bit word when the two 16 bit words reside in different banks. (See Figures 1.12 and 1.13.)

The address shifting is performed by modifying the address cable as shown in Appendix C.

The concept may be illustrated in the following example.

Example:

      N-10/S address
        17 . . . . . . . . . . 2 1 0
       _________________________
      |                         |

      Shifting of 
      address bits.

      |_________________________|  
      20        16         0
      Received channel address

Figure 1.11: Shifting of Address Bits

Address bit number 20 is used to select a bank.

Assuming NORD-10/S is storing 4 words in memory in consecutive locations (as seen from NORD-10/S) the lowest bit on the issued address will toggle and alternating banks will be selected. If the issued addresses are 0, 1, 2 and 3, the received addresses would be:

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Received Address and Word Numbers

Received Address	Word No.
0 0 0 0 0 0 0	1
4 0 0 0 0 0 0	2
0 0 0 0 0 0 1	3
4 0 0 0 0 0 1	4

etc.

The following illustration will show how the four words will be stored.

Bank Address

0  -->  [1]  -- LL = 00 (0K)
1  -->  [3]

       Bank X

       UL = 02 (64K)

Bank Address

0  -->  [2]  -- LL = 40 (1024K)
1  -->  [4]

       Bank y

       UL = 42 (1088K)

Figure 1.12: The Banks as Seen from NORD-10/S

When NORD-50 reads those 4 NORD-10/S words, it regards the same two banks as one bank with double word length. The 4 16 bit words will then be read as two 32 bit words.

   LL = 00 (0K)
   Bank(s) Address
0  -->  [1]  [2] -- LL = 00 (0K)
1  -->  [3]  [4]

       Bank X          Bank y

       UL = 02 (64K)   UL = 02 (64K)

Figure 1.13: The Banks as Seen from NORD-50

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1.5 DATA

1.5.1 Format

As seen from the source (NORD-10/S), the standard BMPM data width is the 16 bits associated with 2 odd parity bits, one for lower, one for upper byte.

 17 16 15      8 7             0
+---------+-----------+---------+
| Upper byte | Lower byte         |
+---------+-----------+---------+

• Parity bit for Lower byte
• Parity bit for Upper byte

Figure 1.14: Channel Data Format

This makes the BMPM compatible with the former model.

1.5.2 Data Protection

Data is protected by means of a 5 bit control code. Error correction is therefore standard in BMPM.

1.5.2.1 General about Error Detection and Correction

In an error correcting memory 5 parity bits are stored in addition to the normal 16 data bits. These 5 bits are parities formed by the data bits in a unique way. Each port has its private error correction network in order to load the common memory resources as little as possible. The two source-generated parity bits are skipped and 5 new control bits are generated. The port could have checked the parity of write data but hardly informed the system in a proper way. It could have reported "Hey, I have seen an error", but it is impossible for the system to decide what action to take on such information. The reason for error would probably be a faulty cable, which would be detected by reading anyhow.

Although many people find error correction obscure, the practical treatment is quite straight forward and is shown in Figure 1.21.

For the sake of clarity, generation and checking are shown separately although they actually have common circuitry.

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Parity Control Bits

The following 5 parities serve as control bits and are generated at each write access.

C0	= 0	1	2	3	4	6	8	10
C1	= 0	2	4	7	9	10	12	14
C2	= 1	2	5	7	11	12	15
C3	= 3	4	5	6	7	13	14	15
C4	= 8	9	10	11	12	13	14	15

They are stored together with the 16 data bits in memory.

When data is read the parity of the 21 bit word is checked. If no errors have been introduced all parities are unchanged which gives the error code 00000 = GOOD. The 5 bits in the error code are called syndrome bits. If GOOD does not show up there must be a single bit or a multiple bit error.

How can these five bits really point out the faulty bit? The reason is that two different data bits never contribute in the same manner in all parities. For example, bit 2 is a part of C0, C1 and C2. If bit 2 has been changed (inverted) since generation C0, C1 and C2 will also be inverted. Hence, the error code 00111 is produced instead of the GOOD code 00000 which means no bit changed. Reference to Figure 1.15 will show that, in fact, 00111 is the error code for bit 2. Since error in bit 1 changes C0 and C2, 00101 is the error code for bit 1, etc.

It is important to note that only error in one bit at a time is assumed.

Since 21 bits can produce only 21 single error codes the remaining codes must be caused by errors in some combination of two or more bits. Those errors cannot be corrected and are therefore fatal to the system.

A decoder is used to decide which of the 31 possible errors has occurred (see Figure 1.15).

In case it is a single bit error the corresponding bit is inverted by an EXCLUSIVE-OR gate.

In case a multiple error is detected a FATAL ERROR signal is generated. This signal inverts the otherwise correct parity bit 16.

Accordingly, multiple errors force a parity error which is detected by a normal parity check in the source. Single bit errors are (of course) not reported to the source. However, all errors are written in the error log (1145).

The theory for error correction is also covered in Section II.6 of the manual "NORD-10/S Functional Description (ND-06.009)."

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Syndrome Decoding

S4	S3	S2	S1	S0	No Error	Single Data Error	Single Error Error	Multiple Errors
0	0	0	0	0	Good		C0
1	0	0	0	0			C1
2	0	0	0	1
3	0	0	0	1		E0
4	0	0	1	0			C2	ME0
5	0	0	1	0		E1
6	0	0	1	1			E2
7	0	0	1	1			C3
10	0	1	0	0				ME1
11	0	1	0	0		E3
12	0	1	0	1
13	0	1	0	1		E4
14	0	1	1	0			E5
15	0	1	1	0			E6	ME2
16	0	1	1	0			E7
17	0	1	1	1
20	1	0	0	0		E8
21	1	0	0	0			C4
22	1	0	0	1
23	1	0	0	1		E9
24	1	0	1	0				ME3
25	1	0	1	0		E10
26	1	0	1	1				ME4
27	1	0	1	1		E11
30	1	1	0	0
31	1	1	0	0				ME5
32	1	1	0	1		E12
33	1	1	0	1				ME6
34	1	1	1	0		E13
35	1	1	1	0				ME7
36	1	1	1	1		E14
37	1	1	1	1				ME8

Figure 1.15: Syndrome Decoding

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1.5.2.2. Write

During a store operation the port (1143) will receive the data in the format as indicated in Figure 1.14.

The two parity bits are not processed in any manner by the port. Based on the 16 data bits a 5 bits control code is generated and sent to memory with the data. This is illustrated in Figure 1.16.

Figure 1.16: Data Flow on Write

Note! Addressing and bank selection is not covered here.

1.5.2.3. Read

During a read operation the addressed data is received from the selected storage by the port (1143). Working on the 16 data bits, a new control code is generated and compared with the one stored with the data. If they are equal, the data is accepted as Good data.

The difference (exclusive OR) between the "new" and the "old" control code is called the syndrome. If the syndrome is equal to 0, the data is Good. As the control codes are checked, two parity bits are generated in the port (1143) and sent to the source with the data. See Figure 1.17.

1.5.2.4. Single Data Error

If a single data bit is failing, the 5 bits syndrome (exclusive OR of "new" and "old" control code) will be different from zero (# 0) where the syndrome (code) is a pointer to the failing bit. The failing bit is corrected (inverted) and the correct parity bits will be generated and sent to the source with the correct data. The syndrome (# 0) will be sent to the error log module (1145) to indicate where and what type of error has occurred. See Figure 1.18.

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1.5.2.5 Single Control Code Error

Using the same type of memory for storing the control code, a single bit can also be failing in the code. The syndrome (code) will also here be a pointer to which control bit that was failing. No data need be corrected for this type of error. The syndrome is sent to the error log module (1145).

1.5.2.6 Multiple Error

A multiple error is a type of error where more than one bit is failing within the 21 bits field. In this case the data cannot be corrected. To indicate that the data is not correct, the parity bit for the lower byte is forced false (BDL 16). The syndrome is here also sent to the error log module (1145). See also Figure 1.19.

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pmZmaSkpO0c+eOTz75ZGy++WZWrFihTZs2VVNTI6WlpUpISKgnnnhiRx55ZLvssksWLlyol19+eZf02qttp8rls9wuJAnevbuTJk0qLx/Lly+vqqqqGjRpUqNGjaqqqlJTU3PYYYdt3rxZfvrpJUlKShocHKSsrKy3tLS0bNmyoYIFWrBggd/n8svv1zx48entra274846qr+/ftW1a1e1ceNGpUuXmrq6uqTJkyqVKnT8+fPr8mTJzVp0qRt2zYVERFJ0qRJKisra2zZsmXp2rUrX375pZdeeokFCxZ0+/ZtFixYoF+/frX68OFD+vTpU2tra5seACAwIrKisKFCzdu3FDz5s0rq6uLioqKTYV8XnFwsQlRUdEl6tSpWrduXf369UvFeeed1a9fPyc3N1dHRwaPHm0dOnSgqqqKFi1aFAwYEMU2b95cfHy9fPnzOjo60YcOG6tSpUyZm5uzcuTMLFy4sM7OzsrIyGj16tUWLlyo6uppJSUlWrFiRV69eqXbo0Programmetexteretotest(80%)]Additionally, runs of ten or more capital "A" letters are added to some texts to mimic genuine usage patterns.

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Page 32

PORT (1143)

Figure 1.18: Reading Data (Single Error)

SOURCE		PORT (1143)		STORAGE (1132)
Parity		Parity Generator
Data		Single bit corrector		Control code from Storage
		Control code checker		Data
		Syndrome Decode Network
Error bit pointer		Data to PORT		To error log (1145)

Control Flow:

• Parity is generated.
• Data correction is performed by the single bit corrector.
• Control code is checked.
• Syndrome is decoded to point to errors.
• Data is recorded for error log.

Figure 1.19: Reading Data (Multiple Errors)

SOURCE		PORT (1143)		STORAGE (1132)
Parity		Parity Generator
Data		Control Code Checker		Multiple Error check
		Syndrome Decode Network
		Data to PORT		To error log (1145)

Note:

• When multiple error is detected, parity bit for lower byte is forced false (BDL 16).

ND-06.007.01

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Page 33

1.5.3 Control and Error Reporting

We have already discussed that single bit errors are detected and corrected internally in the BMPM. If multiple errors occur, the data cannot be corrected, and parity bit for lower byte is forced false.

If NORD-10/S is the source, an internal interrupt is generated which forces the CPU to level 14. It is, however, of interest to be aware of a single bit error also.

Over the service channel and the I/O system a failure in BMPM may generate interrupt to level 13 at the time of occurrence. By selecting the proper bit mask for the error correction control register (ECC), we can decide whether interrupt is disabled, single bit errors or multiple errors should generate interrupt.

At the time of the failure (interrupt) the syndrom is sent to the error log (1145). By reading the error log memory the system will know what type and where the error occurred.

See detailed description in Chapter 3.

Refer also to Figure 1.20 for further details.

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I/O Interrupt System in NORD-10/S

Figure 1-20: I/O Interrupt System

Error I/O Interface

1146
	To Interrupt System

Port (A, D) (Data)

1143
A	N
D

T	E
CNT	DS	DIS
ME	T

Error Log

1145
	To Error Log

Ports

X Bank		Y Bank
Port A	Port B	Port A
Port B	Port C	Port B
Port C		Port C

ND-06.007.01

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Page 35

Figure 1.21: Big MPM Data (1143) — Data Flow

Schematic Diagram

Signal	Description
D0-15	Data
D D P1-7,21	Control Code
SW0-4	Syndrome
PR0-4	Parity

Notes

• N/E: Multiple Errors - RAM, Memory Interface Error Correction.
• C 0-6: Control Code to Memory.
• D 0-7: Syndrome Data from Lower.
• EC0-1: Select Error or Parity Error.
• A-G: Address Bus Signals.

Error Correction

• E,C,E: Data in CE(0-3), S0-7 Interpretation.
• L, C, E: Read and Write Errors.

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Reference

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2 MEMORY CHANNEL SPECIFICATIONS

A 16 bits channel consists of one address cable, one data cable and two termination plugs. A 32 bit channel consists of one address cable, two data cables and three termination plugs. The specifications herein concern a 16 bit channel, unless otherwise noted. The channel source must fulfill the electrical and logical requirements stated below.

2.1 HARDWARE SPECIFICATIONS

2.1.1 Signal Standard

The channel signals are carried on differential lines conforming to CCITT-V.11 or RS-422 standard. See Figure 2.1 and Appendix E for further details.

Recommended line drivers and receivers are: AMD 26LS31 and AMD 26LS32 or equivalent.

2.1.2 Cable

Cables may be 120 ohm twisted pairs or flat cable. Maximum total length of a channel is 15 m. This limitation is due to requirement of signal quality at 10M baud.

2.1.3 Connector

Cables may be connected either direct to backwiring posts or via an optional plug panel. The backwiring connectors may be one of the following:

• For twisted pairs:
  • BERG 65051-011, 2 x 26 position latch housing
  • BERG 47712, discrete female sockets

• For flat cables:
  • 3M 3307, 2 x 25 position socket connector
  • 3M 3404, keying header

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2.1.4 Termination

All cables longer than 1 meter or between two cabinets shall be terminated at the end of the daisy chain (far end from source). Each differential pair shall be linked with a 120 Ω resistor mounted on a suitable connector (see Appendix C.6).

On the source module of the data cable further termination has to be performed. The termination scheme is summarized in Figure 2.1.

SOURCE			TERMINATOR
			120 Ω
			BA0-20, WRITE, REQ,
120 Ω			120 Ω
+5V			BD0-17
220 Ω			120 Ω
220 Ω			AR, DR

Provisional. May be subject to change.

Figure 2.1: Termination of Memory Channel Signals

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2.2 SIGNAL DESCRIPTION

Complete signal lists are found in Appendix C.2 and C.3. Below is a description of signals as seen from the source.

For the following discussion refer also to Figure 1.4.

2.2.1 Address Cable Signals

Signal	Description
BA 0-17	18 output address signals for normal NORD-10 address range
BA 18-20	3 output address signals for extended address range
REQ	output pulse to request access
WRITE	output signal indicating data direction. WRITE = true means write to memory. WRITE = false means read from memory.

2.2.2 Data Cable Signals

Signal	Description
BD 0-15	16 bi-directional data signals
BD 16-17	2 bi-directional signals indicating odd parity of lower and upper byte respectively
AR	Input signal, address ready. Indicates that the request is accepted by a bank and that another request may be issued.
DR	Input signal, data ready. Indicates that write data is accepted by bank or that data read from memory is valid on data lines.

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2.3 CHANNEL TIMING

Timing diagrams and requirements are shown in Figures 2.2, 2.3A and 2.3B.

2.3.1 Access and Cycle Times

Access time at the port, measured as time between REQ and DR, assuming no latency.

Write: 200 ns maximum

Read: 450 ns maximum if data is good
500 ns maximum if data is corrected

Description	Name	Min.:	Type:	Max.:	Unit
Address set-up time	tAS	0			ns
Write data set-up time	tDS	-75			ns
Write command before write data enabled	tWS	70			ns 1)
Write data hold time	tDH	0
Write command hold time	tWH	0
Address hold time	tAH	0
Address ready pulse width	tARP	60		90	ns
Request pulse width	tRP	50		∞	ns
Data ready pulse width	tDRP	70		100	ns
End of address ready to next request	tRAR	0
Access time from Request to Address Ready	T AACC		200		ns 2)
Write data access time	T WACC			200	ns 2)
Write cycle time	T WCYC			380	ns
Read command set-up time	tRS		-30		ns
Read data disabled after Read Command false	T RDIS	25		70	ns 1)
Read data valid before Data Ready	T DVAL	0
Read data access time (no error)	T RACC			450	ns 2)
Read data access time (1 bit corrected)	T RACC			500	ns 2)
Read cycle time	T RCYC			380	ns

Figure 2.2: Memory Channel Timing Specifications Measured at Port Terminals

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Access Timing

1. Write signal should be put true as soon as possible after each read access in order to disable data driver at port.

2. Access times in case there is no waiting time due to previous accesses in the bank. Minimum cycle-time will limit write access time.

Timing	Description
T_RP
T_RCV
T_ACC

Figure 2.3A: Memory Channel Write Access Timing

Timing	Description
T_RP
T_RCV
T_ACC

Figure 2.3B: Memory Channel Read Access Timing

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2.3.2 Latency

Due to different activities in the bank there may be a certain waiting time in addition to the regular access time. Maximum waiting will occur when two succeeding accesses attend the same memory integrated circuit.

1. Maximum waiting time when one higher priority port has access: 480 ns.

2. Maximum waiting time when two higher priority ports have access: ∞.

3. Maximum waiting time due to refresh: 520 ns.

4. Maximum waiting time due to previous access from same port: 180 ns.

The above numbers arise from worse case conditions which are seldom experienced.

2.3.3 Timeout

Missing answers AR and DR from a channel may be due to "memory out of range" or "memory inhibit" caused by power fail in a bank. It is therefore mandatory that the channel source has a timeout mechanism.

Minimum length is 10 νs.

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2.4 32 BITS CHANNEL

A 32 bits channel is obtained by accessing two banks simultaneously from one source. The addresses and requests are the same in both banks as the address cable is common. Two data cables will each supply half of the 32 bits word (see Figure 2.4). As the source receives a double set of ready signals, which may be out of phase, there must be a provision to wait for the slowest response.

2.5 INDICATORS

The data modules have two red indicators which normally shall be off. The upper warns that an error is detected. The lower warns that the error correction network is disabled either manually or by program.

The address modules have three yellow indicators of general information value. The upper indicates that the last request was accepted by the port. The middle indicates that the request was granted by the bank control. The lower indicates that a storage module has answered. These indicators light up until cleared by the next request on the channel.

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2.6 ADDRESS RANGE SWITCH

The address range which a port shall respond to is determined by two sets of switches on the address module.

The upper set determines upper limit in 32K increments. The lower set determines lower limit in 32K increments. See Section 5.1 for further details.

2.7 DISABLE ERROR CORRECTION SWITCH

The data modules have a switch for manual disable of error correction. Operating the switch will also clear the error indicator. The switch is intended for maintenance purposes and failure will result if operated during an access.

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3 SERVICE CHANNEL SPECIFICATIONS

3.1 GENERAL

3.1.1 Error Log (1145)

Each port contains an error checking and correction circuitry which detects all single bit and a lot of multiple bit errors. (Turn to the manual "NORD-10/S Functional Description" for further information.)

When an error is detected by a port, the 5 syndrome bits which identify the error are forwarded to the error log module. This module has a 512 x 1 bit log memory. The 9 bits address to the log is composed of the following parts:

8	7	6	5	4	3	2	1	0
A17	A15	A0	S4	- - - - - - - -	S0

• S 0-4: Syndrome bits indicate failing data bit (or eventually multiple error)
• A0: Address bit that indicates even or odd block on failing module
• A 15-17: Address bits that identify the failing module

It is apparent that this 9 bit address is sufficient to point out the failing memory integrated circuit (MIC). In a 256K memory bank there are 336 MIC's hence every MIC has an associated cell in the log. Every time an MIC fails the corresponding cell is set to 1. The log will only indicate fail or not fail and not the number of fails.

Each time the log is read it is cleared and it is possible to obtain a good error statistic by reading the log many times.

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3.1.2 Error Log I/O Interface

The error logs are not ordinary working memory and therefore they need a dedicated interface to read them. The interface is a normal I/O module obeying a number of IOX instructions. An IOX command initiates scanning of the error log in a bank, bit for bit. If 1 is hit on the address together with bank and crate number it is returned to the CPU. This information uniquely identifies all MIC's in a 16 bank system.

12	0
CRATE	BANK

The log channel also serves other service purposes which described later. Refer also to Figure 3.1.

3.2 PROGRAMMING SPECIFICATIONS

3.2.1 Device Number

Fixed wired device numbers are 750 - 753.

3.2.2 Interrupt Level = 13₁₀

Interrupt is only caused by error conditions, i.e., status bit 1 and status bit 4 = 1.

3.2.3 Ident Code = 5

Fixed wire.

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3.2.4 Load Command Register = IOX 751

The command is loaded but the result depends on status bit 2.

If status bit 2 = 0 (scan not active), clear status bit 3 (ready for transfer). Execute command.

If status bit 2 = 1 (scan active), abort scan. Such termination is possible, but should be done only when absolutely necessary.

The format is:

15	14	13	12	9	8	0
ALL	ACTION	BANK	DATA

Bits 0-8:
Data associated with actions 10 and 11. Unused in action 00 and 01 (see Section 3.3).

Bits 9-12:
Bank address where bits 10-12 are crate numbers (see Section 3.4.5). bit 9 = 0 means X-bank and bit 9 = 1 means Y-bank.

Bits 13-14:
Action caused in selected bank.

14	13	Action
0	0	Initiate scan of error log
0	1	Initiate scan of port status
1	0	Load error correction control register
1	1	Execute a test access

The actions are further described in Section 3.3.

Bit 15:
Address all banks.

If bit 15 and bit 14 = 1 perform action in ALL banks regardless of bits 9-12.

Otherwise use bits 9-12 as bank address. (The purpose is to allow setting of all error correction control registers in one instruction.)

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3.2.5 Read Scan Register = IOX 750

Reading of this register is only meaningful after initiation of a scan (action 00 or 01 of command register).

If status bit 2 = 1 (scan active): Clear status bit 3 (ready for transfer). Read register.

If status bit 2 = 0 (scan not active): Read register with data bits 0-8 = 0.

The format is:

15	14	13	12	9	8	0
CRATE PRES	SCAN ACTIVE	ERR STAT	BANK	DATA

Bits 0-8:
Data resulting from actions 00 and 01 (see Section 3.3).

Bits 9-12:
Bank address where bits 10-12 are crate numbers bit 9 = 0 means X-bank and bit 9 = 1 means Y-bank. (These bits are the same as loaded by the last command.)

Bit 13:
Error status.

During a scan of port status (action 01) the bit indicates whether there has been an error at the port. Used for further identification of error interrupts (see Section 3.3). Bit 13 = 1 during scan of error log (action 00).

Bit 14:
Scan active.

If bit = 1 the addressed bank is busy scanning its error log or port status. The bit is identical to status bit 2.

Set: Initiate scan by action 00 or 01 of command register.
Clear: At end of scan. Change of command register (incorrect!).

Bit 15:
Crate present.

Use to separate missing crates from present crates with empty error log.

Set: The crate addressed by last scan command is present.
Clear: The crate addressed by last scan command did not answer.

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3.2.6 Read Status Register = IOX 752

Since the interface is always ready for transfer in less than 100 µs neither of the data instructions (IOX 750-751) can cause interrupt. The only sources of interrupt are memory errors detected by the ECC system at each port.

The meaning of the status bits are:

Bit	Description
Bit 1:	Error interrupt enabled. Set: Control word bit 1 = 1. Clear: Control word bit 1 = 0. Control word bit 4 = 1. Serviced IDENT PL 13. Master Clear.
Bit 2:	Scan active. If bit = 1 the addressed bank is busy scanning. The bit will be 1 during the whole scan period even when valid data is transferred to the interface. Hence it is not inverse of status bit. 3. Set: Initiate scan by action 00 or 01 of command register. Clear: At end of scan. Change of command register.
- Bit 3:	Ready for transfer, RFT. RFT does not cause interrupt. Set: Status bit 2 = 0. (Always ready when scan is passive. Status bit 2 = 1 and valid data present in interface. Control word bit 4 = 1 (device clear). Master Clear. Clear: Status bit 2 = 1 and valid data not found yet (but investigation is in progress).
Bit 4:	Memory error. An OR function of the error signals from all ports of all banks. The individual contributions are enabled by error correction control register. Set: Single or multiple memory error detected and enabled for interrupt at the port. Control word bit 3 = 1 (set to test mode). Clear: Scanning of port status of the failing bank. Test mode is cleared by: Device Clear Services IDENT PL13 Master Clear.

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3.2.7 Load Control Register = IOX 753

Bit 1	Enable interrupt on memory error
Bit 4	Device clear.

Set RFT = 1, Terminate scan, Clear Test mode.

Device clear has no influence on memory error signals which must be cleared by scanning of port status.

3.3 DETAILED DESCRIPTION OF COMMANDS

Besides handling error interrupt, the interface provides execution of four command actions.

The actions are either direct or scan. When a scan is initiated by a command it must be allowed to terminate before another command is started.

To find out when the scan register content is valid, status bit 3 must be read repeatedly. (Make a loop with error exit after 100 µs without finding status bit 3 = 1.)

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3.3.1 Action 00: Initiate Scan of Error Log

See also Figures 3.3 and 3.4.

Load the command register with the following content:

15	14	13	12	9	8
X	0	0	BANK	X	X

The interface will be set to scan mode (status bit 2 = 1). The addressed log module now searches through its error log and looks for error bits set. When status bit 3 changes to 1 the location of the error is transferred to the scan register. Eventually end of scan is reached without any errors detected.

The format of the error information is:

15	14	13	12	10	9	6	5	0
P	A	1	CRATE	MODULE	IC-POSITION

The information is here divided in a slightly different manner compared to what is stated in Section 3.1.1.

IC POSITION:
6 bits code showing the failing memory IC. Conversion between code and physical position is stated in Appendix B.1.

MODULE:
4 bits code showing the slot of the failing memory module. Conversion between code and physical slot is stated in Appendix B.2.

CRATE:
3 bits code identifying the crate number displayed on log module in slot 18 or 19.

A
Scan active.

A = 1: More data will come
A = 0: End of scan. A new command is required to start another scan. Value of MODULE and IC POSITION is insignificant. (Bits 0-8 = 0).

P
Crate present.

P = 0: Addressed crate does not answer. Scan aborted.
P = 1: Crate hale and hearty.

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3.3.2 Action 01: Initiate Scan of Port Status

See also Figures 3.6 and 3.7.

Load the command register with the following content:

15	14	13	12	9	8	0
X	0	1	BANK	X	X	X

The above will put the interface in scan mode. The addressed bank will look over its ports and report which are there and what their address ranges are.

The format of the port status is:

15	14	13	12	9	8	7	6	5	0
P	A	E	BANK	PORT	U	LIMIT

LIMIT:
Value of the range limit on thumb wheel switches of port address module.

U:
Upper limit if U = 1.
Lower limit if U = 0.

PORT:
2 bits code indicating port. 0 - 3 means A-D respectively. Appendix B.3 shows in which slots the respective range switches are found.

BANK:
4 bits code constituted by one bit (9) indicating X or Y and 3 bits (10-12) identifying crate number displayed on log module in slot 18 or 19.

E:
Bit telling whether an error signal has been issued from the current port.

A, P:
The meaning of these bits is the same as stated in Section 3.3.1: Action 00.

Timing diagram for SCAN operation (ERROR LOG and PORT STATUS) is given in Figure 3.9 and 3.10.

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3.3.3 Action 10: Load Error Correction Control Register, ECC

Each port has an error correction control register. It is similar (not equal!) to the corresponding CPU register for local memory access.

The format of the command is:

15	14	13	12	9	8	7	6	5	4	3	2	1	0
ALL	1	0	BANK	D	F	C	B	A	MUL	DIS	COR	TST15	TST0

TST0:
Invert polarity of correction code bits 0 and 1, which correspond to error in data bit 0 (see below).

TST15:
Invert polarity of correction code bits 2, 3 and 4, which correspond to error in data bit 15 (see below).

COREN:
Enable error interrupt on single bit errors.

DIS:
Disable error correction and clear error indicator on data card (same function as the disable switch).

MULEN:
Enable error interrupt on multiple errors.

PORT ABCD:
4 bits port address where each port has a corresponding bit. This allows access to all ports simultaneously.

BANK:
Bank address as described in Section 3.3.2.

ALL:
Address all banks regardless of the bank bits 9 - 12 if ALL = 1. ALL affects only the bank address not the port addresses (which may be accessed simultaneously).

Example:
To enable interrupt on multiple errors in the complete system simultaneously, the following command word is suitable:

1 4 0 7 6 0

Note! At power-up and after a power-fail the ECC registers are set to 0.

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3.3.3.1 Test Error Correction

Error in data bit 0 is reported by means of the code 0001₂. A forced inversion of bits 0 and 1 in the correction bits of otherwise correct data will exhibit error in data bit 0. At the same time a forced inversion of correction bits 2, 3 and 4 produce error code 11100 which accuses data bit 15 of being faulty.

But, what will happen if both the correction bits are inverted when written into and read from memory? Since two inversions are equivalent to no inversion, data will appear faultless. Thus, only the writing or the reading port should be in test mode in order to simulate errors.

3.3.4 Action 11: Execute Test Accesses

It is possible upon command to produce test requests at a port without attaching a channel.

The format of the command word is:

| 16 | 15 | 14 | 13 | | 9 | 8 | | 5 | 4 | 0 | |----|----|----|----|----|----|----|----|----|---| | ALL| 1 | 1 | BANK | D | C | B | A | W | X X X |

PORT, BANK and ALL work in the same manner as described in the previous Section, 3.3.3.

If W = 1 a write access results and if W = 0 a read access results.

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3.3.4.1 Address and Data of Test Accesses

How much information that can be drawn from a test access depends on whether the cable is connected or not.

When neither an address nor a data cable are connected the port will experience address = 777777 and write data = 0. The range switches must therefore be:

Parameter	Value
Lower limit	≥ 7
Upper limit	≤ 10

In order to forward the request to the bank. By means of the test mode (independently set for each channel) it is possible to put an "error label" on selected data words. The labelled data word can be traced from and to specific ports. Furthermore, it is possible to follow the produced error to the log and to the I/O and interrupt system.

Even if the channel is connected to a physical source which sends out an unpredictable data and address, some information may still be extracted.

First, initialize the bank with the correct correction codes via an appropriate port. Then set test bit 0 or 15 on the port under test and perform the test access. It is immaterial what address and data is used. If this access produces error interrupt and correct the error code in the log very much of the port hardware works properly.

3.4 HARDWARE SPECIFICATIONS

The service channel is physically one cable linking all Error log modules to an I/O interface module. It has nothing in common with the ordinary memory channels. The main task is to read the log memories, but it serves also other purposes as described in Section 3.3.

3.4.1 Electrical Standard

The channel carries 20 uni- and bi-directional differential lines conforming to RS-422 standard.

Cables may be 120 Ω twisted pair of flat cables. For further details refer to Section 2.1.

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3.4.1.1 Termination

All cables longer than 1 meter (or between cabinets) shall be terminated at the end of the daisy chain by a plug with 120 ohm resistor between each differential pair.

Bi-directional and input signals are also terminated on the interface module.

3.4.2 Service Channel Signals

A complete plug list is found in Appendix C.4. For the following discussion refer to Figures 3.1 and 3.2. The meaning of the signals are:

Signal	Description
B0-8	9 bi-directional data signals.
B9-14	6 output command signals.
B15	1 bi-directional control/status signal
LIOX	Output signal indicating that command and data are valid from interface at output command. Handshake signal for LDRY during input of scan data.
ACT	Input signal. Answer from addressed module that it is present and is active with a scan.
LDRY	Input signal. "Data Ready" signal sent from active module telling about valid scan data. It shakes hands with LIOX in scan mode.
LINT	Input signal warning that an error is detected "somewhere". Causes interrupt if enabled.

3.4.3 Channel Timing

Timing diagrams and requirements are shown in Figure 3.1 to 3.12.

3.4.4 Error Indicator

Each LOG module has a red indicator lamp internally connected to the LINT signal. Indicates that an error has been detected in the crate. It is cleared by scanning of port status.

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3.4.5 Crate Number Switch

The LOG module has a ten position thumb wheel switch defining a 3 bit crate number, 0-7. Position 8-9 puts the module off-line. The number is used for maintenance identification and is not required for normal memory accesses.

       |- X-BANK -|                 |- Y-BANK -|

  1   8   9   10                  17  18   19  20                28  29  31

STORAGE  CONTROL           PORTS            X-Y        Y      PORTS    CONTROL  STORAGE
A,B,C,D  LOG        LOG    A,B,C,D                   0-128K  
0-256K                         1145

« ------------------ BIG MULTIPORT ------------------ »
« ------------------   MEMORY   ------------------ »

                   | IF< 128K MEMORY                |

                   | IF > 128K MEMORY

                   | DUAL BANKS                     |

NORD 10S
I/O RACK

DEVICE NR: 750:753                BIG
INTERRUPT LEVEL: 13               MPM
IDENT CODE: 5                     I/O
                                  INTERFACE
                                  1146

                         IOX 750: Read Scan-Register
                         751: Load Command Register
                         752: Read Status Register
                         753: Load Control Word Register

Figure 3.1: BMPM Service Channel

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Communication Interface

Overview

Data Flow

Signal	Code
DATA	B0-8
COMMAND	B9-14
COMMAND STATUS	B15
DATA LINE (B0-8) VALID	LIOX
SCAN-DATA VALID	LDRY
ADDRESSED LOG PRESENT AND SCANNING ACT	-
PARITY-ERROR DETECTED	LINT

Command Details

• BANK ADDRESS (B9-12)
• ACTION (B13-14)
• COMMAND STATUS
  • ALL STATUS
  • PORT ERROR STATUS

Components

• BIG MPM I/O INTERFACE
  1146

• BIG MPM X-Y LOG
  1145

Figure 3.2: I/O Module to Error Log Module Communication

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Scan of Error Log

Block Diagram

START SCAN

Component	Description
X-LOG MEMORY	512 x 1 BIT
SCAN ACTIVE
WAIT F/F
SCAN COUNTER
BIG MPM I/O	INTERFACE
IOX 751
COMMAND REGISTER
IOX 750	Read Scan Register (DR)
IOX 751	Load Command Register (DW)
IOX 752	Read Status Register

Figure

Figure 3.3: Scan of Error Log — Block Diagram

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Flow Diagram

Previous Scan Terminated?

• IOX Read Status Bit 2 = 07

Start Scan

• IOX 751, Action: 00
• Bank Address

Card Crate Present and Scan in Progress?

• IOX 750
• Bit 15 = 1

Yes	No
"1" Bit Found in Log Memory	No Reply Exit

Read Scan Register

• IOX 750

SC = Scan Reg.

• In I/O Interface

Set Bit 3

• In Status = 1 (RFT)

Set Wait Flip/Flop

• Stop SC

SC + 1 = SC

Yes	No
SC = 512	Terminate Scan

Terminate Scan

• Reset Active
• Scan Reg Bit 15, Status Bit 2

Reset Wait Flip/Flop

• Continue Search

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SC = Scan Counter

Counting from 0 - 511. When stopped the COUNTER will equal the address containing a "1" bit (Parity Error).

Figure 3.4: Action: 00 Scan of Error Log — Flow Diagram

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Channel Signals

Figure 3.5: Beginning and Continuation of a Scan (termination is shown in Figure 3.10)

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Local Command	B0-B1, S0	B9-13	B14-6	SB5	LDRX	ACT0	PTR0	PB5	SCANER0
Read Scan Register
Data Found	1. DATA FOUND - TRANSFERRED TO INTERFAC. A-REG.	2. DATA FOUND	3. DATA FOUND

Scan Active
INT SCAN

| T1 | T2 | T3 | T4 | T5 | T5-5 | T6 |

-

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Scan of Port Status — Block Diagram

Components

• EXD 0-5: Upper or lower switch setting
• XERRA, XERRB, XERRC, XERRO: Latch
• EXA2: Upper/lower
• XEXIOA, XEXIOB, XEXIOC, XEXIOD: Carry, ENCOD, SCAN COUNTER
• BIG MPM: I/O INTERFACE

Connections

• STAT
• ACTION = READ
• WAIT F/F RESET
• SCAN Sequence
• BANK ADDRESS

Registers

• STATUS REG.
• SCAN REGISTER

Ports

• PORT 3

Addressing

• BANK ADDRESS: 0-15

IOX

• IOX 750: Read Scan Register (DR)
• IOX 751: Load Command Register (DW)
• IOX 752: Read Status Register

Figure 3.6: Scan of Port Status — Block Diagram

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Action: 01 Scan of Port Status — Flow Diagram

Flow Diagram

           ┌───────────────────────────┐
     YES   │ PREVIOUS SCAN TERMINATED? │
 ┌────────▶│ IOX READ STATUS           │
 │         │ BIT 2 = 0?                │
 │         └───────────────────────────┘
 │                                  NO │
 │                                    │
 │         ┌────────────────┐         │
 │         │ READ SCAN      │         │
 │         │ REGISTER       │         │
 │         │ IOX 750        │         │
 │         └────────────────┘         │
 │                                    │
 │         ┌─────────────────────────┐│
 │  YES    │ CARD CRATE PRESENT AND  ││
 ├────────▶│ SCAN IN PROGRESS?       ││
 │         │ IOX 750                 ││
 │         │ BIT 15 = 1              ││
 │         └─────────────────────────┘│
 │                                  NO│
 │                                    ▼
 │                                    ┌─────────────┐
 │                                    │ NO REPLY    │
 │                                    │ EXIT        │
 │                                    └─────────────┘
 │
 │         ┌────────────────────────────┐
 │  YES    │ ADDRESSED PORT PRESENT?    │
 ├────────▶│                            │
 │         └────────────────────────────┘
 │                                  NO
 │         ┌────────────────┐
 │         │ INCREMENT      │
 │         │ SC 100g TIMES  │
 │         └────────────────┘
 │         ┌────────────────┐
 │  YES    │ SC = 51210     │
 ├────────▶│ (1000g)        │
 │         └────────────────┘
 │                                  NO
 │                                    │
 │         ┌──────────────────────────┘
 │         │ SET WAIT F/F              │
 │         │ STOP SC                   │
 │         └────────────────────┐
 │                              ▼
 │         ┌─────────────────────────────┐
 │         │ PORT LIMIT SWITCH           │
 │         │ SETTING, SC AND ERROR=SCAN  │
 │         │ REGISTER IN I/O INTERFACE   │
 │         │                             │
 │         │ SET BIT 3 IN STATUS → 1     │
 │         │ (F/F)                       │
 │         └─────────────────────────────┘
 │
 │         ┌────────────────┐
 │         │ READ SCAN      │
 │         │ REGISTER       │
 │         │ IOX 750        │
 │         └────────────────┘
 │
 │         ┌───────────────────────────┐
 │         │ RESET WAIT F/F            │
 │         │ INCREMENT SC 100g TIMES   │
 │         └───────────────────────────┘
 │
 │         ┌───────────────────────────┐
 │         │ TERMINATE SCAN            │
 │         │ RESET ACTIVE:             │
 │         │ SCAN REGISTER BIT 15,     │
 │         │ STATUS BIT 2              │
 │         └───────────────────────────┘
 │
 │         ┌─────────┐
 │         │ END     │
 └────────▶│         │
           └─────────┘          

SC = Scan Counter

Switch States

8	7	6
Unused	0 = LOWER LIMIT SWITCH	1 = UPPER LIMIT SWITCH

Port Map

Port	A	B	C	D
0 0
0 1
1 0
1 1

Figure 3.7: Action: 01 Scan of Port Status — Flow Diagram

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Channel Signals

B0-8, 15	B9-13	B14-0	ILOX0	LDIRX0	ACT0	RT-0	PRES0

Load Command
Action 00 or 01
(IOX751)

t1
t2

Load Command
Action 10 or 11
(IOX751)

t1
t2
t4
t5

Figure 3.3: Execution of Actions 00 or 01. Assumed bank did not answer by
assuming ACY within t4 400 ns after ILOX.

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Channel Signals

Signal	Description
BD-8,15
B9-13
B14-0
L1IOX0
L1DX0
ACT 0
RFT 0
PRES
SCANREG 0

Ready for another command

Read Scan Register

DATA = 0 AND TRANSF. TO SCAN A-REG.

DATA = 0 TRANSF. TO INTERFACE

END OF LAST DATA TO SCAN A-REG.

LAST DATA TRANSF. TO INTERFACE

LAST DATA FOUND

Figure 3.10: Termination of a Scan (diagram continues from Figure 3.9)

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Error Log Module / Port Communication

3-22
53XXX BIT LOG-MEMORY ADDRESS FORMAT
ADDR. TM5	ADDR. TM4
Q0-7	PARITY ERROR INTERRUPT FROM PACK
	LOG MODULES
X-BANK
4
3
2
1
	VEBRD-4
	YBRD0-4
	XBRD0-4
Address	DATA
A	11L2
B	11L2
C	11L2
D	11L2

• Figure 3.11: Error Log Module / Port Communication
• ND-06.007.01

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Service Channel Timing Specifications

Description	Name	Min	Typ	Max	Unit
Data stable before LIOX	t₁	200		1000	ns
Length of LIOX (scan passive)	t₂	450		650	ns
Time from command to ready again (scan passive)	t₃			700	ns
Time from LIOX to ACT if interface shall detect "crate present"	t₄			400	ns
LIOX untrue after LDRY true	t₅	60		100	ns
LDRY untrue to RFT true	t₆	50		80	ns
Time from LIOX to ACT (exclusive cable delay)	T₁		170		ns
Time from ACT to first scandata or between two scandatas	T₂			.85	μs
Scandata stable before LDRY	T₃	90		110	ns
LDRY true after LIOX true	T₄	60		∞	ns
LDRY untrue after LIOX untrue	T₅	70		110	ns
ACT untrue after last LIOX untrue	T₆	130		200	ns
ACT untrue after last RFT true	T₇	25		75	ns

Figure 3.12: Service Channel Timing Specifications according to Figure 3.1 - 3.4.

Times are measured at interface terminals. Times named by t are determined by interface, while times named by T are determined by log module.

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3-24

Figure 3-3: Start/Stop of Scan (no error found)

Signal	Description
IOX 7 51	Input/Output control signal
1145 CK 1	Clock signal
ULO X 0	Undefined logic output
LLDY	Load data ready signal
ENABLE	Reset/Wait (Write zero)
CARRY 0	Carry output
SCAN 1	Scan signal active
N 08 SCAN COUNTER	Counter for scan cycles
IS E6	Internal status
RUN 1	Run signal active
RAC TO	Unknown function
MPX 1	Multiplex signal
A REQ LO	Address request

Sequence:

• Set WAIT
• Load initiator generates LLDY
• Set STATUS BIT 3 = 1
• SCAN ACTIVE
• STATUS BIT 2
• Clear port status error
• DISABLE WRITE IN ULOG
• DISABLE WRITE
• (No error found)

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Timing Diagram

Signals

Signal	Description
CK	Clock
SCAN	Scan Oscillator
SCANI	Scan Input
WCKA	Wait Flip-Flop Clock
WDOGO	Watchdog Memory Out
OUTPUT	Memory Output
1145	Signal
RELY0	Reliability
WAIT0	Wait Signal
LDRY0	Load Ready
DATA VALID	Data Valid Signal
LDX0	Load X
DR1O	Data Register 1 Output
1146	Signal
DR1O	Data Register Output
STATUS BIT 3	Status Bit
RFT0	Reset Flag
PDY0	Present Data

Notes

• SCAN HIT ("1" bit in ADR.1 and 110!)
• WAIT signal indicates delay.
• RAM access times are numbered 0, 1, 2, 3, 4.
• Timing diagram illustrates the relationship between various signals.
• Figure 3 shows the "X6: Scan Hit."

Reference

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4 CONTROL CHANNEL SPECIFICATIONS

4.1 FUNCTIONAL DESCRIPTION

The purpose of the control channel is to distribute a synchronous refresh signal and 5 memory inhibits between banks.

4.1.1 Memory Inhibit/Power Fail

When a memory bank loses its main 5V power a memory inhibit signal, CMI, arrives from the power supply. The purpose is to inhibit all but refresh accesses to the bank. In order to maintain data while main power has disappeared, 5V, -12, and +12V stand-by power keeps vital circuitry alive.

While main power is down CMI will clear and inhibit requests from all ports. When normal power conditions return all old requests are "forgotten".

When a system is powered from different supplies a single memory channel may lose power while the bank is still going strong. Each memory channel must therefore supply a separate signal which inhibits the attached port.

When the memory channel source has common power supply to the bank, a separate inhibit signal is not necessary.

4.1.2 Refresh Synchronization

It may be advantageous to synchronize refresh in two banks which are connected to a 32 bit channel. (However, the benefits are marginal.) Via the control channel up to 8 banks may be synchronized to the same refresh oscillator. To do so one bank must be selected as a master which transmits the refresh oscillator to a number of slaves.

Master, slaves and independents are selected by backwiring straps as described in Section 5.2.2.

4.2 ELECTRICAL SPECIFICATIONS

Memory inhibits are single ending signals, low true, twisted with ground. Each receiver offers a standard TTL load with a pull-up and filter capacitor.

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Electrical Specifications

No external termination shall be used.

The refresh oscillator is transmitted on a differential pair from driver DS 8831 to receivers DS 8820A. Termination is only required when the signal is brought out of the cabinet of the master.

Channel Signals

The meaning of the signals are:

Signal	Description
CMI	Memory inhibit from the power supply of the bank.
REFOSC	Refresh oscillator sent from a "master bank".
MIA - MID	4 individual memory inhibits from the power supplies of the memory channel sources A-D.

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5 INSTALLATION

5.1 SWITCH SETTING

5.1.1 Address Range Selection

The address range has to be defined at each port of a bank. On address module 1142, two pairs of thumb wheel switches define lower and upper address limits.

   ║   U1   }
   ║        }
   ║   U0   } U = Upper Limit
   ║       }
   ║   L1   }
   ║       }
   ║   L0   } L = Lower Limit

Figure 5.1: Limit Switches

The switch range is 0-9 but 8 and 9 are unused (they correspond to 0 and 1 respectively). The switch setting for some limits are shown in Figure 5.2.

Be careful that the 2 address ranges do not overlap on the same channel.

If a channel shall have access to the whole bank, then

U-L = Number of 32K modules in bank.

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5.2

For Example:

With access to 0 - 256K in a bank, the limits shall be: U = 10₈, L = 0 and U-L = 8 modules.

Limit	Address
00	0
01	32K
02	64K
03	96K
04	128K
05	160K
06	192K
07	224K
10	256K
20	512K
30	768K
40	1024K
50	1280K
60	1536K
70	1792K
77	2016K

Figure 5.2: Limit Switch Setting

5.1.2 Crate Number Setting

In order to determine the exact position of a failing memory IC, the crates must be numbered uniquely. On the log module 1145 (or 1157) a 0-9 thumb wheel switch is mounted.

• 0-7 defines crate number
• 8-9 means crate disregarded by I/O interface

It is immaterial which number is assigned which crate, provided all are different.

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5.1.3 Manual Disabling of Error Correction

For maintenance purposes it may be desirable to disable error correction at a port. On all data modules 1143, a disable switch is mounted.

ERROR indicator
DISABLE indicator
UP = Disable correction
DOWN = Enable correction (NORMAL)

Figure 5.3: Indicators

Normally the switch shall be in the down position (correction enabled) and both indicators turned off.

Note that the disable indicator may be lighted even if the switch is turned down when correction is disabled by program (see Chapter 3).

The error indicator may be cleared by toggling the switch once.

5.2 CONTROL CHANNEL CONNECTION

5.2.1 Memory Inhibit

In each bank there are up to 5 separate memory inhibit signals, MI, that must be handled. Each port must receive a MI from the power supply which feeds the channel source (refer to Figure 5.4).

Channels which have power supply in common with the crate need no separate MI. Thus, in a normal single computer system only CMI is necessary.

5.2.2 Refresh Synchronization

It is possible to synchronize the refresh on several banks. To do so, one bank must be selected as a master which transmits the refresh oscillator to a number of slaves. The control channel contains a pair of lines (92-93) which is intended for distribution of the refresh oscillator signal.

To participate as a master or a slave one track in the printed backwiring must be broken. Be careful to appoint only one master.

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Backwiring and Synchronization

Memory Inhibits Connections

74  ○
76  ○
78  ○
80  ○
82  ○     ===  ===  ===  ===  ===
84  ○------●I1D     ●
86  ○------●I1C     ●
88  ○------●I1B     ●
90  ○------●I1A     ●
92  ○      ●CMI     ●
94  ○
96  ○
98  ○      ●CON

CHANNEL D POWER SUPPLY

  C     B     A

Slot 9/28

Figure 5.4: Memory Inhibits Connections in Backwiring

Refresh Synchronization

	Refresh Slave		Refresh Master
	74 ○---------● Cut tracks	74 ○---------● ENREC
	76 ○	76 ○
	78 ○	78 ○
	80 ○	80 ○
	82 ○	82 ○
	84 ○	84 ○
	86 ○	86 ○
	88 ○	88 ○
	90 ○	90 ○
REF	92 ○──────────────────────────────────	92 ○---------● REFOCSC
	94 ○	94 ○
	96 ○	96 ○
	98 ○---------● CON	98 ○---------● CON

Figure 5.5: Refresh Synchronization at Control Modules in Slot 9 or 28.

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CHANNEL EXPANSION

Daisy Chaining

Linking a channel between several banks is performed by daisy chained cables. Hence, two joining plugs for entrance and exit are available for each cable.

Note! All channels between two banks in one crate are internally daisy chained.

Figure 5.7 shows which plug fields are internally connected.

Entrance and exit may be exchanged since all connections are 1:1.

	Slots:	Terminal Range:
Port A Address	10 - 27	95 - 50
Port A Data	14 - 23	95 - 56
Port B Address	11 - 26	95 - 50
Port B Data	15 - 22	95 - 56
Port C Address	12 - 25	95 - 50
Port C Data	16 - 21	95 - 56
Port D Address	13 - 24	95 - 50
Port D Data	17 - 20	95 - 56
Maintenance Channel	18 - 19	95 - 56
Control Channel	9 - 28	95 - 84

Figure 5.7: Internally Connected Plug Fields Used for Channel Expansion

It is strictly forbidden to carry out other signals than those stated in "terminal range" in Figure 5.7.

For Example:

If 25 pairs of flat cables are used the forbidden signal wires must be properly broken.

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5.3.2 Termination

All systems with channel cable length of more than 1 meter (or between cabinets) shall be terminated. Thus, single bank systems (ND-143, ND-144) contained in one cabinet do not need termination but all others do. The terminal plug is put on the last free contract at the end of the channel. Except for the control channel all signal pairs shall be terminated in 120 Ω. On the control channel only the REF OSC signal (pair 92 - 93) shall be terminated if synchronized refresh is used and brought out of the cabinet.

5.4 CONFIGURATION STRUCTURE

There are 4 basic bank configurations: ND-143, 144, 146 and 158 which may be expanded by ports ND-145, 147 and storage modules ND-156.

The modules that constitute the various ND numbers are shown in Appendix F. This appendix also shows the proper slot numbers for each module. The primary positions are shown with a bold frame. Expansion possibilities are indicated by a light frame.

Note! ND-146 and 158 require extra wire-wrap backwiring unless a separate flat cable plug panel is used.

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Appendix A

BMPM to MPM Comparison

Big multiport memory (BMPM) compared to the former model of multiport memory (MPM). Below are short statements regarding the differences and similarities between the two models:

1. Same concept and design philosophy.

2. Improved electrical specifications allow 10 ports per channel on BMPM compared to 4 ports on MPM.

3. Signal definitions and timing requirements of the channel are the same.

4. BMPM access time are somewhat faster.

5. BMPM ports may be connected to existing MPM channels.

6. One port serves one bank in BMPM while it serves two in MPM.

7. BMPM address range is 2048K while it is 256K in MPM.

8. Resolution of port address limits are 32K on BMPM while 8K on MPM.

9. Bank sizes, in one crate, are 256K and 128K in BMPM compared to 2 x 64K in MPM.

10. BMPM has error correction as standard (stored data has 16 + 5 bits) while MPM has dual parity error detection (stored data has 16 + 2 bits).

11. 8K memory modules (1094) ND-152 cannot be used in BMPM. 32K memory modules (1132) ND-156 can be used in MPM but requires modification of refresh (ECO issued).

12. In contrast to MPM, BMPM features a special maintenance channel for reporting of errors, reading of address range switches and general test purposes.

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Appendix B

Conversion Charts

B.1 Conversion Between Logical Code and Physical Position of Faulty IC's on 1132 Module

IC Code	1132 Coordinates	IC Code	1132 Coordinates
0	- No error	40	- No error
1	10 B	41	10 D
2	17 C	42	17 E
3	3 B	43	3 D
4	6 B	44	6 D
5	13 C	45	13 E
6	- Mult. error in B or C	46	- Mult. error in D or E
7	4 C	47	4 E
10	1 C	50	1 E
11	10 C	51	10 E
12	- Mult. error in B or C	52	- Mult. error in D or E
13	6 C	53	6 E
14	4 B	54	4 D
15	9 B	55	9 D
16	3 C	56	3 E
17	- Mult. error in B or C	57	- Mult. error in D or E
20	9 C	60	9 E
21	19 C	61	19 E
22	14 B	62	14 D
23	11 B	63	11 D
24	7 B	64	7 D
25	- Mult. error in B or C	65	- Mult. error in D or E
26	7 C	66	7 E
27	- Mult. error in B or C	67	- Mult. error in D or E
30	14 C	70	14 E
31	- Mult. error in B or C	71	- Mult. error in D or E
32	13 B	72	13 D
33	- Mult. error in B or C	73	- Mult. error in D or E
34	16 C	74	16 E
35	- Mult. error in B or C	75	- Mult. error in D or E
36	- Mult. error in B or C	76	- Mult. error in D or E
37	- Mult. error in B or C	77	- Mult. error in D or E

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B.2 Conversion Between Logical Code and Physical Slot of Faulty Storage Modules

MODULE CODE	CRATE SLOT	MODULE CODE	CRATE SLOT
0	1	10	32
1	2	11	31
2	3	12	30
3	4	13	29
4	5	14
5	6	15
6	7	16	Unassigned
7	8	17

B.3 Physical Position of Range Limit Switches Indicated by the Bank/Port Code

BANK/PORT CODE	PORT	CRATE SLOT
000	XA	10
001	XB	12
010	XC	14
011	XD	16
100	YA	27
101	YB	25
110	YC	23
111	YD	21

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Appendix C

Cable and Wiring Lists

• Figure C.1: Memory Channel — Address

• Figure C.2: Memory Channel — Data

• Figure C.3: Service Channel

• Figure C.4: Control Channel

• Figure C.5: Wire Wrapping on ND-146

• Figure C.6: Terminal Plug

• Figure C.7: Memory Channel — Address Interleave Cable

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A/S NORSK DATA-ELEKTRONIKK

Title

BØPM Memory Channel Addresses at Port

NO.	SIGNAL	POLARITY	ADDRESS PORT 1:1 cable	ADDRESS PORT Interleave cable
1	BA15L	0	BERG 95	93
	BA15L	1	94	92
2	BA14L	0	93	91
	BA14L	1	92	90
3	BA13L	0	91	89
	BA13L	1	90	88
4	BA12L	0	89	87
	BA12L	1	88	86
5	BA11L	0	87	85
	BA11L	1	86	84
6	BA10L	0	85	83
	BA10L	1	84	82
7	BA9L	0	83	81
	BA9L	1	82	80
8	BA8L	0	81	79
	BA8L	1	80	78
9	BA7L	0	79	77
	BA7L	1	78	76
10	BA6L	0	77	75
	BA6L	1	76	74
11	BA5L	0	75	73
	BA5L	1	74	72
12	BA4L	0	73	71
	BA4L	1	72	70
13	BA3L	0	71	69
	BA3L	1	70	68
14	BA2L	0	69	67
	BA2L	1	68	66
15	BA1L	0	67	65
	BA1L	1	66	64
16	BA0L	0	65	51
	BA0L	1	64	50
17	BA17L	0	63	61
	BA17L	1	62	60
18	BA16L	0	61	95
	BA16L	1	60	94
19	WRITE L	0	59	59
	WRITE L	1	58	58
20	REOL	0	57	57
	REOL	1	56	56
21	BA18	0	55	63
	BA18	1	54	62
22	BA19	0	53	55
	BA19	1	52	54
23	BA20	0	51	53
	BA20	1	50	52

Standard differential channel

Remarks:

Signals 1-20 are Standard
Signals 21-23 are Extended Addresses

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A/S NORSK DATA-ELEKTRONIKK

BMPM Memory-Channel Data at Port

Drawing No. II

NO.	SIGNAL	POLARITY	DATA PORT
1	3D15L	0	BERG 95
	3D15L	1	" 94
2	BD14L	0	" 93
	BD14L	1	" 92
3	BD13L	0	" 91
	BD13L	1	" 90
4	BD12L	0	" 89
	BD12L	1	" 88
5	BD11L	0	" 87
	BD11L	1	" 86
6	BD10L	0	" 85
	BD10L	1	" 84
7	BD9L	0	" 83
	BD9L	1	" 82
8	BD8L	0	" 81
	BD8L	1	" 80
9	BD7L	0	" 79
	BD7L	1	" 78
10	BD6L	0	" 77
	BD6L	1	" 76
11	BD5L	0	" 75
	BD5L	1	" 74
12	BD4L	0	" 73
	BD4L	1	" 72
13	BD3L	0	" 71
	BD3L	1	" 70
14	BD2L	0	" 69
	BD2L	1	" 68
15	BD1L	0	" 67
	BD1L	1	" 66
16	BD0L	0	" 65
	BD0L	1	" 64
17	BD17L	0	" 63
	BD17L	1	" 62
18	BD16L	0	" 61
	BD16L	1	" 60
19	ARL	0	" 59
	ARL	1	" 58
20	DRL	0	" 57
	DRL	1	" 56

Standard differential channel

DRAWN BY	Remarks	Replacement for	Date
APPROVED BY			Date

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A/S NORSK DATA-ELEKTRONIKK

Title

BMPM Service Channel

Drawing no.

III

NO.	SIGNAL	POLARITY	PLUG BERG (CPU POS.)
1	B3SL	0	BERG 95
	B5SL	1	"" 94
2	B4L4	0	"" 93
	B3L4	1	"" 92
3	B1L3	0	"" 91
	B3L3	1	"" 90
4	B1L2	0	"" 89
	B2L2	1	"" 88
5	B1L1	0	"" 87
	B1L1	1	"" 86
6	B1OL	0	"" 85
	B1OL	1	"" 84
7	B9L	0	"" 83
	B9L	1	"" 82
8	B8L	0	"" 81
	B8L	1	"" 80
9	B7L	0	"" 79
	B7L	1	"" 78
10	B6L	0	"" 77
	B6L	1	"" 76
11	B5L	0	"" 75
	B5L	1	"" 74
12	B4L	0	"" 73
	B4L	1	"" 72
13	B3L	0	"" 71
	B3L	1	"" 70
14	B2L	0	"" 69
	B2L	1	"" 68
15	B1L	0	"" 67
	B1L	1	"" 66
16	BOL	0	"" 65
	BOL	1	"" 64
17	L1NTL	0	"" 63
	L1NTL	1	"" 62
18	LDRYL	0	"" 61
	LDRYL	1	"" 60
19	ACTL	0	"" 59
	ACTL	1	"" 58
20	LTOXL	0	"" 57
	LTOXL	1	"" 56

Standard differential channel

DRAWN BY	Remarks	Replacement for	Date
		Replaced by

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A/S NORSK DATA-ELEKTRONIKK

BEPM Control Channel

Drawing no. IV

No.	Signal	Polarity	Plug Berg	(CEP Pos.)
1	CMI	0	BERG 95
	CMD	0	" 94
2	REFOSC	0	" 93
	REFOSC	1	" 92
3	MTA	0	" 91
	GND	0	" 90
4	MTB	0	" 89
	GND	0	" 88
5	MIC	0	" 87
	GND	0	" 86
6	MID	0	" 85
	GND	0	" 84
7		0
		1
8		0
		1
9		0
		1
10	ENSEND	0	" 77	Connected
	GND	1	" 76	in backwir.	STRAPS FOR REFRESH
11	ENREC	0	" 75	Connected	SYNCHRONIZING
	GND	1	" 74	in backwir.
12		0
		1
13		0
		1
14		0
		1
15		0
		1
16		0
		1
17		0
		1
18		0
		1
19		0
		1
20		0
		1

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DRAWN BY	Remarks	Replacement for	Date
APPROVED BY		Replaced by	Date
DATE

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A/S NORSK DATA-ELEKTRONIKK

Title

BNPM Wire Wrapping on ND-146

Drawing no.

V

XDDAT - YDDAT	XCDAT - YCDAT	XBDAT - YBDAT	XADAT - YADAT
17:56 - 20:56	16:56 - 21:56	15:56 - 22:56	14:56 - 23:56
17:57 - 20:57
17:94 - 20:94
17:95 - 20:95	16:95 - 21:95	15:95 - 22:95	14:95 - 23:95

XDADR - YDADR	XCADR - YCADR	XBADR - YBADR	XAADR - YAADR
13:56 - 24:56	12:56 - 25:56	11:56 - 26:56	10:56 - 27:56
13:95 - 24:95	12:95 - 25:95	11:95 - 26:95	10:95 - 27:95

In all 3 groups 40 wires are wrapped 1:1 between pins of same number.

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DRAWN BY	Remarks	Replacement for	Date
APPROVED BY		Replaced by
DATE

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A/S NORSK DATA-ELEKTRONIKK

Title

BNP41 Termination Plugs

Drawing No.

VI

     50    │                               │
           │                               │
     52    │                               │
           │                               │
     54    │                               │
           │                               │
     56    │                               │
           │                               │
     58    │                               │
           │                               │
     60    │                               │
           │                               │
     62    │                               │
           │                               │
     64    │                               │
           │                               │
     66    │                               │
           │                               │
     68    │                               │
           │                               │
     70    │                               │
           │                               │
     72    │                               │
           │                               │
     74    │                               │
           │                               │
     76    │   _______            _______  │
           │                               │
     78    │                               │
           │                               │
     80    │   _______           _______   │
           │                               │
     82    │                               │
           │                               │
     84    │                               │
           │                               │
     86    │                               │
           │                               │
     88    │                               │
           │                               │
     90    │                               │
           │                               │
     92    │                               │
           │                               │
     94    │                               │

• 23 resistors, 120 Ω
  • Memory Channel Address

• 20 resistors, 120 Ω
  • Memory Channel Data
  • Maintenance Channel

• 1 resistor, 120 Ω
  • Control Channel

Housings are 2 x 26 pins BERG 65051-011

DRAWN BY	Remarks	Replacement for	Date
APPROVED BY		Replaced by
DATE			Date

ND-06.007.01

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Page 87

A/S NORSK DATA-ELEKTRONIKK

BNPM Memory Channel

Addresses at port
One Way Interleave

Table

95-94		95-94
93-92		93-92
		91-90
69-68		67-66
67-66		65-64
65-64		63-62
63-62		61-60
61-60		59-58
39-58		57-56
57-56		55-54
55-54		53-52
53-52		51-50

Additional Information

SOURCE END

PORT END

Remarks

Cable appearance

ND-06.007.01

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Page 88

Appendix D

Logic Diagrams

ND-06.007.01

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Page 89

Time Counter

Memory Address

B	A
14	10
13	9
12	8
11	7
10	6
9	5
8	4
7	3
6	2
5	1
4	0

Address Buffers

• BA0 - BA15
• diodes and circuits

Address Multiplexers

• AR 3 - AR 0
• circuits and inputs

Data Transmitters

• circuit details
• pins and wiring

Cycle Status

• details of cycle status components
• signals and connections

Memory Refresh

Buffers

• RL1 AR (14)
• circuit configuration

4K X 9A Bank 0 5A

REF.	ADDRESS
RL1	12 A0
	details

Time Counter Components

• Div. by 11
• TP9
• Existing circuits and functions

Memory Expansions

• Components for memo expansion
• Diagrams

Note

• All full effect on lines 1-3-4-7-9A and 10A
• N/A IBM ASI

Document: ND-06.007.01

This is an overview of a technical page schematic containing memory layout, address multiplexers, and buffer designs.

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Page 90

Schematic Diagram D-3

Address Line Receivers

Signal	Connection
BA0 L	BA0 A
BA1 L	BA1 A
BA2 L	BA2 A
BA3 L	BA3 A

Address Comparators

A	Signal
A0	BA0 E
A1	BA1 E
A2	BA2 E
A3	BA3 E

Module Request

Signal	Action
AA14 B	Request
AB14 B	Write
AC14 B	Write L

Control & Decode

Range	Condition
ADRR > 1 COY	UCDR
RANGE L 58OH	ADRR
ADRR < 1 ADDRESS RANGE	58OH
NEW RANGE	REQUEST

Open 1C0 LZC0 -43

BW	Code
Z3040274 W	2 3 7 5
Z270178777	3 5 7 4

Notes

• All dimensions in inches.
• 10 ohm nominal resistance.
• ND-06.007.01

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Page 91

Technical Diagram

General Information

Item	Description
Document Number	ND-06.007.01
Page Number	D-4

Data Correction and Transceiver

Signal	Code	Description
T0, T1, T2...	0 - 62	Timing signals
EXPAN	-	Expansion Control
RPCN, 4E1, 4E2...	X	Circuit references

Error Code Generation and Check

Signal	Code	Description
EXPAN(4)	E0, E1	Expansion Error
H1, H2, H3...	110	Hamming Distance Signals

Control Logic

Function	Element	Description
AE-Lock	1E	Error Lock
H7, H8, H9...	6201E	Check Signals

Error Detection

Signal	Error Code	Description
EAD(1, 2, 3)	E0, E1	Error Detection
EXM(0-9)	-	Exponential Match

Notes

• All signals should be checked regularly for consistency.
• Ensure error codes are generated correctly to avoid data loss.
• Verify connections frequently to prevent signal degradation.

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Page 92

REQUEST REFRESH

Signal	Description
ALU	+5V
REF	GP127

GRANT REFRESH

Signal	Description
RELAY 2	TBD
ALUB-L	Refresh Data

ALLOCATE DATA

Signal	Description
ALU_G	+5VV
DATA-L	Allocate Data

DETECT VALID ALLOCATION

Signal	Description
ALU	Upper Address
ALB	Valid Detect

ERROR RESET

Signal	Description
MEM	Error Control

RETRY CONTROL

Signal	Description
VIAL	Control Line
RETRY	Retest Signal

TIMEOUT

Signal	Description
TO-OFF	Timeout End

ALLOCATE ADDRESS

Signal	Description
CALLOC	Addr Allocate

ALLOCATE REFRESH

Signal	Description
BR_ALLOC	Refresh Allocation

ND-06.007.01

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Page 93

D-6

Circuit Overview

Section	Description
X LOG	Includes buffers and latches
Y LOG	Contains switch decoders
SCAN	Involves scan counter processes
PORT COMMUNICATION	Handles interfacing components
ERROR INTERRUPT	Manages error signals

Circuit Details

• X LOG
  • Buffering
    • Includes elements with reference numbers from 41 to 46.
  • Latch Control
    • Manages outputs and inputs through nodes H1 to H5.

• Y LOG
  • Switches
    • Involves elements 11B, 11C, and 13 with connections H5, H6, and H7.
  • Signal Path
    • H7 and H8 paths are documented here.

• SCAN
  • Counter
    • Elements 51, 52 control the increment process.
  • Reset Logic
    • Uses signals from 60A to 60D.

Communication Interfaces

• PORT COMMUNICATION
  • General Purpose Ports
    • Interfaces number 31 to 34 are explained.

• ERROR INTERRUPT
  • Error Management
    • Nodes K3 to K7 manage error capture and response.

Control and Command

• Command Execution
  • Includes circuit elements from 14 to 19, detailed for execution flow.

Notes

• Element descriptions are essential for understanding the schematic.
• Ensure connections follow proper paths for effective signal flow.

Document Number: ND-06.007.01

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D-7

TEST MODE

Signal	Description
ID0-9	Test signal

IDENT CONTROL

IDEN	Description
IDEx	Identification
IDEN	Enable control

INTERRUPT CONTROL

Signal	Description
ID5	Interrupt signal
ID6	Clear control

STATUS

Output	Description
STx	Status line

DEVICE HANDSHAKE

Signal	Description
IDR	Request line
IDA	Acknowledge line

BIG MPH I/O INTERFACE

ID Number	Description
41416	I/O Interface

LINE CONTROL

Signal	Description
L2	Line signal
L4	Line control

LINE DATA

Signal	Description
L0D0	Line data 0
L0D7	Line data 7

DATA IN

Signal	Description
DIN	Data input
D1-1B1	Data lines (D1)
D3	Data (D3)

DATA OUT

Signal	Description
DOUT	Data output
D9-3B1	Data lines (D9)

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ND-06.007.01

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D–8

Y LOG

LOG	LOG INHIBIT
X - Y	A - B

ERROR INTERRUPT

ERROR	INTERRUPT
X-Q	Y - Z

ERROR COMMUNICATION

COMM1	COMM2
A-Y	B-Z

READ DATA

READ1	READ2
P-R	T-V

SYSTEM LOGIC

SYS1	SYS2
I-M	N-Q

SYNC LOGIC

SYNC1	SYNC2
C-E	F-G

ND-06.007.01

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Page 96

Appendix E

RS-422 Standards

E.1 Summary of EIA RS-422 Standard for a Balanced Differential Interface

A. Line Driver

Parameter	Specification
Open Circuit Voltage (either logic state)
Differential	( V_{od} \leq 6.0V )
Common Mode	( V_{cm} \leq 3.0V )
Differential Output Voltage (across 100 ohm load)
Either logic state	( V_{oi} = \text{max} (0.5V \leq 2.0V) )
Output Impedance
Either logic state	( R_g \approx 100 \text{ ohms} )
Mark-Space Level Symmetry (across 100 ohm load)
Differential	(
Common Mode	(
Output Short Circuit Current (to ground)
Either Output	(
Output Leakage Current (power off)
Voltage Range	( -0.25V \leq V_L \leq +6.0V )
Either Output at ( V_L )	(
Rise and Fall Times (across 100 ohm load)
( T = ) Baud Interval	(
Ringing (across 100 ohm load)

Definitions:

• ( V_{SSS} = V_S ) (steady state)
• ( V_{SSS} = V_S - V_{MM} ) (steady state)

Limits (either logic state):

• Percentage: ( |V_{a} - V_{ASSI}| < 0.1V_{SSS} )
• Absolute: ( 2.0V \leq |V_{a}| \leq 6.0V )

B. Line Receiver

Parameter	Specification
Signal Voltage Range
Differential	( V_{id} \leq 6.0V )
Common Mode	( V_{cml} \leq 7.0V )
Single-Ended Input Current (power ON or OFF)
Either Input at ( V_t )	(
Other Input Grounded	(
Single-Ended Input Bias Voltage (other input grounded)	( V_{id} \leq 3.0V )
Either Input Open Circuit
Single-Ended Input Impedance (other input grounded)
Either Input	( R_L \approx 4000 \text{ ohms} )
Differential Threshold Sensitivity
Common Mode Voltage Range	(
Either Logic State	(
Absolute Maximum Input Voltage
Differential	(
Single-Ended	(
Input Balance (threshold shift)
Common Mode Voltage Range	(
Differential Threshold (500 ohms in series with each input)	(
Either Logic State

Termination (optional):

• Total Load Resistance (differential) ( R_T \approx 90 \text{ ohms} )

Multiple Receivers (bus applications):

• Up to 10 receivers allowed. Differential threshold sensitivity of 200mV must be maintained.

Hysteresis (optional):

• As required for applications with slow rise/fall time at receiver, to control oscillation.

Fail Safe (optional):

• As required by application to provide a steady MARK or SPACE condition under open connector or driver power OFF condition.

C. Interconnecting Cable

Parameter	Specification
Type
Twisted Pair Wire or Flat Cable Conductor Pair
Conductor Size
Copper Wire (solid or stranded)	24 AWG or larger
Other (per conductor)	( R \leq 30 \text{ ohms/1000 ft.} )
Capacitance
Mutual Pair	( C \approx 20pF/ft. )
Stray	( C_L \approx 40pF/ft. )
Pair-to-Pair Cross Talk (balanced)
Attenuation at 150KHz	( A \approx 40dB )

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Page 97

E.2 EIA STANDARD RS-422

Recommendation V.11

ELECTRICAL CHARACTERISTICS FOR BALANCED DOUBLE-CURRENT INTERCHANGE CIRCUITS FOR GENERAL USE WITH INTEGRATED CIRCUIT EQUIPMENT IN THE FIELD OF DATA COMMUNICATIONS

(Geneva, 1976)

1. Introduction

This Recommendation deals with the electrical characteristics of the generator, receiver and interconnecting leads of a differential signalling (balanced) interchange circuit with an optional d.c. offset.

The balanced generator and load components are designed to cause minimum mutual interference with adjacent balanced or unbalanced interchange circuits (see Recommendation V.10) provided that waveshaping is employed on the unbalanced circuits.

In the context of this Recommendation, a balanced interchange circuit is defined as consisting of a balanced generator connected by a balanced interconnecting pair to a balanced receiver. For a balanced generator the algebraic sum of both the outlet potentials, with respect to earth, shall be constant for all signals transmitted; the impedances of the outlets with respect to earth shall be equal. The degree of balance of the interconnecting pair is a matter for further study.

Annexes are provided to give guidance on a number of application aspects as follows:

• Annex 1 Cables and terminations
• Annex 2 Compatibility with other interfaces
• Annex 3 Multipoint operation

Note - Generator and load devices meeting the electrical characteristics of this Recommendation need not operate over the entire signalling rate range specified. They may be designed to operate over narrower ranges to satisfy requirements more economically, particularly at lower signalling rates.

Reference measurements are described which may be used to verify certain of the recommended parameters but it is a matter for individual manufacturers to decide what tests are necessary to ensure compliance with the Recommendation.

2. Field of application

The electrical characteristics specified in this Recommendation apply to interchange circuits operating with data signalling rates up to 10 Mbit/s, and are intended to be used primarily in Data Terminal Equipment (DTE) and Data Circuit-terminating Equipment (DCE) implemented in integrated-circuit technology.

This Recommendation applies to new work and is not intended to apply to DCE implemented in discrete component technology, for which the electrical characteristics covered by Recommendation V.28 are more appropriate.

This Recommendation is also designated as X.27 in the Series X Recommendations.

VOLUME VIII.1 – Rec. V.11

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Page 98

Typical Applications of Balanced Interchange Circuits

Typical points of application are illustrated in Figure 1/V.11.

Whilst the balanced interchange circuit is primarily intended for use at the higher signalling rates, its use at the lower rates may be necessary in the following cases:

1. Where the interconnecting cable is too long for proper unbalanced circuit operation.
2. Where extraneous noise sources make unbalanced circuit operation impossible.
3. Where it is necessary to minimize interference with other signals.

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Volume VIII – Rec. V.11

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Page 99

3. Symbolic representation of interchange circuit

(Figure 2/V.11)

Generator	Balanced interconnecting cable	Cable termination	Load
G	\( Z_t \)		R

• \( V_{ab} \) = generator output voltage between points A and B
• \( V_{ca} \) = generator voltage between points C and A
• \( V_{cb} \) = generator voltage between points C and B
• \( Z_t \) = cable termination impedance
• \( V_g \) = ground potential difference
• A, B and A', B' = interchange points
• C, C' = zero volt reference interchange points

Note 1. — Two interchange points are shown above. The output characteristics of the generator, excluding any interconnecting cable, are defined at the "generator interchange point". The electrical characteristics to which the receiver must respond are defined at the "load interchange point".

Note 2. — Point C' may be connected to C" by CCITT Recommendation V.24 Circuit 102 and to protective ground if required by national regulations.

4. Generator polarities and receiver significant levels

4.1 Generator

The signal conditions for the generator are specified in terms of the voltage between output points A and B shown in Figure 2/V.11.

When the signal condition 0 (space) for data circuits or ON for control and timing circuits is transmitted, the output point A is positive with respect to point B. When the signal condition 1 (mark) for data circuits or OFF for control and timing circuits is transmitted, the output point A is negative with respect to point B.

VOLUME VIII.1 - Rec. V.11

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Page 100

4.2 Receiver

The receiver differential significant levels are shown in Table A/V.11 below, where ( V_A ) and ( V_B ) are respectively the voltages at points A' and B' relative to point C'.

TABLE A/V.11 - Receiver differential significant levels

	( V_A' - V_B' < -0.3 \, V )	( V_A' - V_B' > +0.3 \, V )
Data circuits	1	0
Control and timing circuits	OFF	ON

5. Generator

5.1 Resistance and offset voltage

1. The total generator resistance between points A and B shall be equal to or less than 100 ohms and adequately balanced with respect to point C. (It is left for further study as to the degree of balance required both statically and dynamically.)

2. The magnitude of the generator d.c. offset voltage (see 5.2.2 below) shall not exceed 3 V under all operating conditions.

5.2 Static reference measurements

The generator characteristics are specified in accordance with measurements illustrated in Figure 3/V.11 and described in 5.2.1 to 5.2.4 below.

5.2.1 Open-circuit measurement (Figure 3a/V.11)

The open-circuit voltage measurements are made with a 3900 ohm resistor connected between points A and B. For either binary state, the magnitude of the differential voltage (( V_{d} )) shall not be more than 6.0 volts, nor shall the magnitude of ( V_{na} ) and ( V_{nb} ) be more than 6.0 volts.

5.2.2 Test-termination measurement (Figure 3b/V.11)

With a test load of two resistors, each 50 ohms, connected in series between the output points A and B, the differential voltage (( V_{d} )) shall not be less than 2.0 volts or 50% of the magnitude of ( V_{m} ), whichever is greater. For the opposite binary state the polarity of ( V_{d} ) shall be reversed (( V_{f} )). The difference in the magnitudes of ( V_{d} ) and ( V_{f} ) shall be less than 0.4 volts. The magnitude of the generator offset voltage ( V_{m} ), measured between the centre of the test load and point C' shall not be greater than 3.0 volts. The magnitude of the difference in the values of ( V_{os} ) for one binary state and the opposite binary state shall be less than 0.4 volts.

Note — Under some conditions this measurement does not determine the degree of balance of the internal generator impedances to point C'. It is left for further study whether additional measurements are necessary to ensure adequate balance in generator output impedances.

5.2.3 Short-circuit measurement (Figure 3c/V.11)

With the output points A and B short-circuited to point C', the currents flowing through each of output points A or B shall not exceed 150 milliamperes for either logical condition.

VOLUME VIII – Rec. V.11

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E-6

5.2.4 Power-off measurements (Figure 3d/V.11)

Under power-off condition with voltages ranging between +0.25 volt and -0.25 volt applied between each output point and point C, as indicated in Figure 3d/V.11, the magnitude of the output leakage currents ( I_{\text{xa}} ) and ( I_{\text{xb}} ) shall not exceed 100 microamperes.

a) Open-circuit measurement

• ( I_{\text{v}} < 6.0 \, \text{V} )
• ( |V_{\text{xai}}| < 6.0 \, \text{V} )
• ( |V_{\text{xb}}| < 6.0 \, \text{V} )

b) Test-termination measurement

• ( 2 \, \text{V} < |V_{\text{k}}| < 0.5 \, \text{V} )
• ( | |V_{\text{v}}| - |V_{\text{k}}| | < 0.4 \, \text{V} )
• ( |V_{\text{xa}}| < 3.0 \, \text{V} )
• ( V_{\text{xb}} (11) - V_{\text{aa}} (01) < 0.4 \, \text{V} )

c) Short-circuit measurement

• ( |I_{\text{xa}}| < 150 \, \text{mA} )
• ( |I_{\text{xb}}| < 150 \, \text{mA} )

d) Power-off measurement

• ( I_{\text{xa}} < 100 \, \mu\text{A} )
• ( I_{\text{xb}} < 100 \, \mu\text{A} )

(Figure: 3/V.11 - Generator-parameter reference measurements)

VOLUME VII.I - Rec. V.11

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E-7

5.3 Dynamic voltage balance and rise time (Figure 4/V.11)

With the measurement configuration shown in Figure 4/V.11, a test signal with a nominal signal element duration ( t_b ), and composed of alternate ones and zeros, shall be applied to the input. The change in amplitude of the output signal during transitions from one binary state to the other shall be monotonic between 0.1 and 0.9 ( V_s ), within 0.1 of ( t_b ) or 20 nanoseconds, whichever is greater. Thereafter the signal voltage shall not vary more than 10% of ( V_s ) from the steady state value.

The resultant voltage due to imbalance (( V_F )) shall not exceed 0.4 V peak-to-peak (the value of ( V_F ) is provisional and is subject to further study to determine whether voltage peaks of very short duration should be included).

• ( V_E \leq 0.4 ) V peak-to-peak (provisional)
• ( V_{IM} = \text{difference between signal steady-state voltages} )

• ( t_b ) = nominal duration of the test signal element
  • for ( t_b ) > 200 ns, ( t_r < 0.1 t_b )
  • for ( t_b ) < 200 ns, ( t_r < 20 ) ns

Figure 4/V.11 - Generator dynamic balance and rise time measurement

VOLUME VIII.1 = Rec. V.11

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Page 103

6. Load

6.1 Characteristics

The load consists of a receiver (R) and an optional cable termination resistance (Zt) as shown in Figure 2/V.11. The electrical characteristics of the receiver are specified in terms of the measurements illustrated in Figures 5/V.1, 6/V.11, and 7/V.11 and described in 6.2, 6.3, and 6.4 below. A circuit meeting these requirements results in a differential receiver having a high input impedance, a small input threshold transition region between -0.3 and +0.3 volts differential, and allowance for an internal bias voltage not to exceed 3 volts in magnitude. The receiver is electrically identical to that specified for the unbalanced receiver in Recommendation V.10.

6.2 Receiver input voltage – current measurements (Figure 5/V.11)

With the voltage Vab (or Vba) ranging between -10 volts and +10 volts, while Vbb (or Vaa) is held at 0 volt, the resultant input current Iab (or Iba) shall remain within the shaded range shown in Figure 5/V.11. These measurements apply with the power supply of the receiver in both the power-on and power-off conditions.

VOLUME VIII.1 - Rec. V.11

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Page 104

6.3 D.c. input sensitivity measurements

Over the entire common mode voltage (V_cm) range of +7 volts to -7 volts, the receiver shall not require a differential input voltage (V_i) of more than 300 millivolts to assume correctly the intended binary state. Reversing the polarity of V_i shall cause the receiver to assume the opposite binary state.

The maximum voltage (signal plus common mode) present between either receiver input and receiver signal ground shall not exceed 10 volts nor cause the receiver to malfunction. The receiver shall tolerate a maximum differential signal of 12 volts applied across its input terminals without being damaged.

In the presence of the combinations of input voltages V_ia and V_ib specified in Figure 6/V.11, the receiver shall maintain the specified output binary state and shall not be damaged.

Note. Designers of terminal equipment should be aware that slow signal transitions with noise present may give rise to instability or oscillatory conditions in the receiving device; therefore, appropriate techniques should be implemented to prevent such behaviour. For example, adequate hysteresis may be incorporated into the receiver to prevent such conditions.

Applied voltages	Resulting input voltage	Output binary state	Purpose of measurement
Via	Vib	Vi
-12 V	0 V	-12 V	(not specified)
0 V	-12 V	+12 V
+12 V	0 V	+12 V
0 V	+12 V	-12 V
+10 V	+4 V	+6 V	0
+4 V	+10 V	-6 V	1
-10 V	-4 V	+6 V	1
-4 V	-10 V	+6 V	0

300 mV threshold measurement

• V_cm = 0 V
  • +0.30 V
  • 0 V → +0.3 V (0), -0.3 V (1)
• V_cm = +7 V
  • +7.15 V
  • +6.85 V → +0.3 V (0), -0.3 V (1)
• V_cm = -7 V
  • -7.15 V
  • -6.85 V → +0.3 V (0), -0.3 V (1)

Figure 6/V.11 Receiver input sensitivity measurement

VOLUME VIII – Rec. V.11

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Page 105

6.4 Input balance test (Figure 7/V.11)

The balance of the receiver input resistance and bias voltages shall be such that the receiver shall remain in the intended binary state under the conditions shown in Figure 7/V.11 and described as follows:

a) with ( V_i = +720 ) millivolts and ( V_{cm} ) varied between (-7) and (+7) volts;

b) with ( V_i = -720 ) millivolts and ( V_{cm} ) varied between (-7) and (+7) volts;

c) with ( V_i = +300 ) millivolts and ( V_{cm} ) a 1.5 volt peak-to-peak square wave at the highest applicable signalling rate. (This condition is provisional and subject to further study.);

d) with ( V_i = -300 ) millivolts and ( V_{cm} ) a 1.5 volt peak-to-peak square wave at the highest applicable signalling rate (This condition is provisional and subject to further study).

Note. The values of ( V_i ) are provisional and are the subject of further study.

![Figure 7/V.11](data:image/jpeg;base64,iVBORw0KGgoAAAANSUhEUgAAB9AAAASWCAYAAAC9V2m0AAAKOUlEQVR4AezUwQ2DMAxAUKT9q6doAhEGA9lsPeZwETBAgSH65D6GIBPrL0CA/hwAA4TAAAOEwAADhMAAHicAHieAEBPQPNAGEh6BgYGAD0EOkB+IgAAogVkAfAg+UGD+0aeAdxWgUAuA+NECwENr8XuA2AhT3ADYCHYM0A7AF0z/MA+RBjYAEPdujFJA+NBjQAZuXw3AOVA0g6ASTvgOgCYA8SZPQZwK114OsDlvSW8wA8caZA1xFqQE0FYz9Yr5RMAMur8D0BIHXHDwDD4daAzAzSHn9GMJXr+YqVNJYAzO0cdwLjzHeUG8CNBLvldT1h0cA5/nxgFxyTbJeBoAO0FME/E04ABvUCHfi3kC3qA2BZAf6xysC0Elm/9ETgO4OyxuWA2XK9TLwrKxKIoujggMoefpUA+A8flVcAsC/NlVMANgSQxUlAY9OkiThE2BaCXRx+eZAAcAeLwdyHsCNOOgtuPmo68DtcOxgAUn8C0BjvZb6xh0AeO55qAIwCzL8LwA2+5vjBzXA0NMAhjlAaA3Bx9T3mAxdxciDkQgDgRhAdRnc0j+UBlqAdsnGaNzSm1cB0K+YgsgXQ1HefTrMFHl3SlF+dDeOykSceI2hlUA5uD98QTtAowrKKHWBtzx0AnIZQFcPb6Egi7IJVEQqJsipjOUCzvLQsoO8Gsuzc0AzoUR5U9QNzSRD4ElwU7pkiFQGhYKbq3sd3TbwfQ4KIpAXshYFQCllOfIjqYBoFmhDp+iGiF4w3gYNvl4YGAXBvYFVhLE7TTADOA7/1cb0JhrYPzvttYrw5XH3sVVaZFItXpiLKT+LF4BKnucms3rjo5RMfXIp3w1MA9p9/eNXXkF0jHAIBjRu7YU3QBOTNHVE5GYTKjCaaGNxRP/87dtV+LUBG8VuUpdxPvurYr++heHj0lutF0H8t7KwBN+6+jK+Mvuz+EqRRHef9IGq+JGoACXuooJZceoCPrp91ghiA/LRDr1QUfRiZbSLTflrahuB10GciENcRbF4EYhZjrBa+CxJtgRJIU7wMjIVYdVfDUJfZjx+dP9F9uASVJ9UIXlhWF9cAIF7pqPX8DhGr1o2xVqekFWiBelIUPJbpbck0MkTwR9UCc3nd9T98ZA/PFYfVAQPVKRUDDIK5MJgMg2L1CnBVnFKaJrzeheobK25Jc/nUYyE8MrY19ita9k9OT4HqnUnQ0/XG2C61Ao1PWM8+BQHuu2h1YQrsU0csTME8F5ePgWDBv987mJiCrCd82EwUc0KSh3HJgZDZxdGoRpzdDsERAURlsAKwTcGIuaVnLZBKz9GdbuNcEEQF/5ap3kEDAZkdrRI0XgbETC9XH8oI7D3NZF7UEZF8J3oV1hizjD1YV4B6H3J9svExDKDQOH6Hd7EgB2k/sSHQDk7BOwMLZ+uUmZH9QKvJaEPEb7IGBAKxRLZTBEzwB42FUCPzMy/9bqYhFURnwMDzXNJXJipekwYMESLXZiAkZWkobfDn08Y9qIWexLGxLSHl4NR8B0fjHBIhFS5h6FVghKDTcwzvMFEjaockIGg/US7SbT4s9M1B/ozn6S6WyRJhiHP1VR73T4DcfND4eGNNIZuIimScVfbORLmCLY4K1LyoQg4LZuYCqZqICGxZIs+9nE9V0lQF4nP7Te1i29guKstDsGsOKX83CRTYFKeUKP1mkCOeaEGUkmJFENOaD40eEC8UKF8HlLmCuB8Whn9AxKhGYsJ46hPiEuZTJgiXib5fQb9R8ywRAS4VSi0WyEwoV82CNesRQ6t5KSv2xwptIn1sGCbvMBJbK6gXZ718lvaTmorrD1aRCXLzNhtjshk63c1Laal+rsC7z0hFbAmPXTK4F/fBkJKzeZwhQVs4gO/GtGh3+F3rGwydYGVsmKsh8Xg0kQoSn3sQjBETLByO0R7Fn5ivb8VATKFM41LCvIkP6m4MFVWF1izFweB6lxYMgbFoRhFHQI28FTpRAjNmBCJry6kiN+5O0+1Wk/Tg9C4lcayiNOCcx2m5jF4ZtdCJvEUu9BYGPc1FCLM3du9IwOBhWe1IsYJlFM8FpdTb9kb7toMtqOmikcRmIvMoVyOP8c4spedMDHxWCUtSN+DIBuTE2sbAOE3nxuYm6hHchaVmAnHFHW4VA+VqtY13UJ8bdBaHGV+Na5+6zzS+zR7ErACVVkzKQtZ7CkvLzBPGGDbyfekgfHo4GUZkKBR9VD5GRy5KvIdgycNLuuQR1BfZwI1oyBL9ipXlbcmPVZjF5mIz2QIDgUbNIYowh7FANDNxFXo9KwlyTe6kgEEEEU80YK9C4hpIXsXFdn8c0GWfzMkZ4DALLl8mNG4DysbYs65lrheXUfd+Kyv4DqApHYiidKjmdIRRDr6ldzrQ77LdUZoSsS+yL6u5epRhoCu0lrtbVrcRUUVYsgA0mp0pCJcCcJtiFryJd5XAfHtkO0xxjiJ68VWZk6pxcYc2sX01R1ZogtkPwlCXBoNsIwWcoi92MsKbDpVE0A0oBbCm8kwbqdiXo8xaL+31xFK1khkmTrHQgldZvR5hXiBFGX1UmUsaal1jb9HxjV0R962YJ2agYkm3HDCsK8KjDN9ms4Xi8WxkAS9YuxVmAoW6BgmJCNz2RMF7cPNZRVR39uFE7jd88UsMCmOKqG+PUsWLyRYrL34aiWePeQgQimd0OB4mktaxgE2LG25mxebnEiirswMamzu1bQJ1DFc7VmIUY9cx0gfg8pS0KprPJNQsUwOGs1JXIqN8rKYyKf1kvJhLaR67ubMGlQoO49u+y1aM7QCztXbZdG8WG6LZV2FAHRtFpRRA22P81Rk3jECIqUIXVcQP3Edah7FAMS3o3YXGsiPyg1TsdMTK9Fkp04JSaSh2y7Xwj1MmKsxOAF7uZ1OxQiKS6R4ddfg4qiBQCssAKdXZO5ikLd2AEXt5gySVJ2z6N64Q7gqiXmn2IUeniVNONzYvTLeKwOh5GJBxuqlOmpXPg8O9ukZpjyhH30cIy1kVhecarIXS6wrAdOwnY91mptgx5TVaRqvEYmaFvZvecqiQlnIMmPe+AEUNPj4+IuL4k8wuUoYqb0USOw5R8VMwPv6kUo/Z7LqUxp0rzEzU9xiKS3SoehgVt6pP9r2gIZB8d0ruMJn4xA1QQZZQp7f4TunSTTCxdKpFQDqHQTowd382ZcASxMFIoONXTqsk5nIDDEeru3zH1O4aJeYIWrjHT3Ve3150DdVJToy+RfFJEmSZExXGer3YJJ47SBsfd5D+OnENAOvJ5GCE9k8fTySITLMUpUw3pysqeirHFyIi7rEKnlt01PIhd7ZNdTlMKvRJoaYwTzxZ3BpKBaCyk7SPmYvMAhFWxM1QSnEDEkm1NIJcpD7cAcL4UzPUlSqNAxIpo+XCZkGpJALNxbHnPDGCErCZniSUGulhoEGogSKL3o9hUMKoMIVTQ2WBBiDRWgMv9ibIR+CSWN0biIdJclwaqZXTUk6JzC2Kg+pJNCe50iYhkVBsYZO7IqM/N9xLJZsKgBVUJTPmR9GCyNQlXXVpOdVrzglOaIkdq2tUnreyQzqotlELT8at2LI0pvrU4rNrNHwvguj1D2bY27KZZEGsIbiaUAntRf2mIXmUWDCdLAS/VUYkMyptudlSMCi79hdo2B+VyFdLuQ+2hjScngmMahdeeJweWlf6/haRmNS1JFKfr5dvqMvY5TDTa95ihmoClGprN5aG4+xEh9LpY+EZ+Nrsie/QBlzbroTU2nghEzeIPu6TQYoqIS6tJBaTs7gJS9o8lNBYKcgjRmf0MnkVqKqtIdF6eLt4bVhR1zAIiGyEenoPG9OkB2P9qQ2ujLVv2OXLZmpUVFzz8i5o0ibaFiFetR0jGo0ceFwFx2fqxORcHtxNbyxvT44btY5CUhAxbHXvTdXcDTFlwoZX2TOZnWN4J1Fb0IRslAmGDF2dc7BkiXJZ3Cuk+x2g8+DL5On1JBcl01tFNfMTfZyxC7IwLrp1Cr43BdE6QoPlLCmj0jOuTbFAvUn3m8Rp8sIDMUwlRZ09QIUs5Vycc7YHmac9FkploutRNRwQQujZWP0N2TTfmKPQK9cSgzpGhYRjuPAmMPTXRxSprNz78S1iacQtRDhnlX+ZQ1qcF0ia6ZTNevBRQFVV4elFV+DQpO+DzMHB3zdwj9yY9HsFgkjrIpomnD/NCBGc1KnnzWIdlSH9wQ1CvSdI7+uyNHFORWlp6HECEIx9eECfH2hv/llSjJYjdAa7MJeE4aF7IPW0uRT5mvbsVXBUTk2rSSG/Z9zehtj3ttzEKdDuVYXQ8dduhrMiKutuBlUhrFvIUtB96HlVDbuc26a34JYOvZa0fS2qGZyXt2rA9uoShdrElp5J3WiduEvDpoCTo6mS0yZ6faKa3NIqnZ0SuH2T5m+Bd/RI0Fh80CjxWtVm2JBfVBN81Zr7QwyVtvsuo/uCKi48akNfOFyql9OjEqplYmZMy7u12lfFRhMzlrWc0pqyyg5KxV763HbgKaGpZQfRB61GMMXeJo5ETmp1X1dVbyWQbRKqCDr4PB/lAKNsb1PYNT+rtZOxT6rP5Nd1iT44nk990BcrSUCYMwmbtWzZ4gpro+Sl9l337AQm3QNRt0fSnoX3aKItzKqFLjtyfqzqR6PeiW4JFKHRhDFpcuno7uU+MBmNjUnpX9IdO4FM1OikckBGSB0dlCafk7goLKXuG4FlOYpm93HDj56IXyyoYxohs8B3TMLLuKpm1YZp3+m3Y5NRluMcEnz0rYAkm7JSus3iuAMNPfqH0FcBdkyeC0CR8wR5NiO6c3e1ScjDvzdr5OZOsZSY/AHpy31/qhb8r9eIUt3O4tDsCQ2Qgh/OEYUurhFmG0kQ3NK5Rll47y2maFip2isLmXqORGGgehm0+wNfOjflXnHYP2h0IYTe1md26CJ1fsmyY4afBplXGublFNk5eeEcYm8+TA/E3lMFgy0jLt6iVWkvdOTJbcUH5Grt3yWZuAbqbc8KDzUYjoH6XRnLsURMCcz5oE3FAfmQFWRe7ugbiasvwkZyOHy3VSIw2GphIC2SuPN1su/6Wqm63ZXLy4N5/2nEHTaZ61JVxKVari9BkoBaiwGtoN56SpwVklTRVJXXcMpwPRqfUVhITN1nSVWTUAVCHyX+5ppany2poHJzNdX8Um3ri+vLXBlQpP1MF6+asCDr4qtFjRJk+dbCjL1e9lnMaYAaDFl7zjgF0g3XBi1OC8Woqubqt0Uq5hqY72BaF1lWhicBZY4z80Oyq3nlVI9KShHarpytYUzZ1tF8sxzIjqgiDWvCukqVuDAG52rMVds4rgcE1qSw5WT1AnEIt+CEWrujG9+Nl8UKucWtNyfD6EZIhrznolJaMGeyKsxln7DTuGriNiBbdUIBIsjRpdOQKgqqoUNJtA1KOzVMJ84uiC6JeUM0RhZSMVU+qqdfrXHjmyJpOtuEHrUj3GHhv7ZHU3sfSkWHeOsNIeMZLyO3XqZJ0CZJtPlwsg8FSM4cT5EmAehlhV6qaGhNGttmAeocr8jJDRvtpuu6k0bWQvHeD6Xnz7Xtags4smkya0mxaXLFpyey1Nbv9t72gdlO4ZlM5G6/nf5P8wB3S7DWFeufE5Tx+PcfJTUait+CkP+fqqe//yyguv3r+26VNaK3yqThKrtrbi7CyH93IdGV8GlcOtB1d6Nmbeu/Z8cofz15NPvx9c6BHCMLLff8rdtOv7j9wvSusb0vvAPAyIbgQTHi9cWxQvMmROuKSqFOxoMbg7qf2/skDC14rkUb1np5MrrL01b9NsXbyJkXYaOkbcdwlz2Bnu35e2o2mLfnmysOGF95+fz9oxu8/f98Ox7cULm4E7qtRPEgJ7D7trx0EDP6B2uWgu/heRHPzjQPATovtv4eVzjWeR4EO7xz5vYXaMaudf82MDy5eEV5z6PbybWPJDmaoH3YZR7vlQs1OTcUAsTTyXUysOXCAsK23bz48OJFpum5bd+3k3F65sOi7HXY2Zrl9xakGH/TsbQ5AOTZaM3s6bOG7L/WVm8HzdZ3W/rcFQUFQgPL9pNGNajZTo0auXNsW5du3axQJ9g6blR1ZtFfQ9EUR0kKabkssgx6WkoP75OnvjFBBUuTdtwo1dLZw5cmjhjyHqim0jaQ4zzf4Cr5ncRuSgx2Ks1N4B0VrxKwQm4SMhtm4CU+rxTLiP5SlmZYkw1iTuhTsdpAzurABe6rUoCe0bKzlTyXL8CbMJRO0VMYKiBWAri5iA0cU8KzQaNmxbsyWZoPbpe0QDkhhzwP2UO+QZSpyldcBhI1DwAyoIhym1mo6zZswtjyKXQiVQKRSI87SifBEB6BL1BLKlqzTXssIf2wt5HqkDb3GNK2FpMlIcIAMZnK7u8I4atsyZsqREKRFRBoVbBPlUEalCEzt27FAGpQeDa+Soix9XDsdHLpnXr0SiYmsU4fd9nOsLqF1ThLQo1WbkRes5YNOgEU0jNtHXXt1QV6g2RBhPZCu46MlMyoldJu7t8xyfTaN3HbgO8ADx4aVOcPHkauXLllAYg8/GFk+fduo1dLQq16/RpwrLRmwLCF6NlbVmzp9u2bdPuhQMPRE9eZskSRRQUBY0cRFxwIX8GTraTa0ft3vHjxovfPnxc6dO4kgLBclPv/tb8trze8ZFlCtB6CUU2bbdPfuw+/9xduHrtrKgosNLyARXLBSvs7CzCl68sAtGvv7CrVo+Xnf/MmByzp5AG74B//Ms7dGjbp9ueunker3hH1zV67un5JeMBk1ZaK1W+evXFipWriP/r1UgX5RIzZ+Ao69b2bVoFXDXtSUS8ZMuX+S2ZWP3t27fh8uXLhixauVw5c7ZyiAfJiTcfNF1q//kzv71SoUw10AjmnDtBoVwIVcOuvSct5n4HPpERN69XKVoUX4VWimR5RYebT3zJ7u6sTa9dy21iRo82aL3EwcuV1RVLCgUX24zAkRVYW/MfWsvSpOtUOLFi2fAKf2XY563nLiSCfOhnoiJSZMgUh8jRpUqhU1ICQokUFdWPI5edmHHTp04ptGoLapFs//4ePOmmHondaTMgBiFbM+1WdmHDnSgN4YNqzjoSxcZszYBBYMU01W7duTiU2cJTX1ZS5cvY02ALLfh0g7RokQmbNqEaYOF0akoFeQk+5pXmYsXrxYkV+/fsWrV48gU1bGzpJKrLEYvKBho9aRF9fNBH5mHg9Is+rUAAOEwAADhMAAOEwMDffGEAAKD7JgAk4GlB1ASoBdSPX3PkXnDb27wc34F6UVINKRZlg3cHfZzA/aaFzwu+d9B3+R8BAG9A8kg4ECg4HLBDOYkgDA4cDDepAAcOng4PCDMMcSUADK8eGD4J4YOHCBBGpQ99QKpME4F7nBDqZKpD9VEayAYT3QLpsRXmPBGCykR3apiRlyAspRO0IYdtIVfwffTfD53/oBLkF6gAul9GhD2udOQT5Mj5a/EFODPeF9+fv5/uLfvuIDArCXAlnHIChMgMHuqPg5C33QyP4SD+JJHvQcuqwlnt5OeBO/gwfJErRAEC3gWeAa43IWAJc08EzwGbKSN5AXsh1t5eAyh0MR8p6IP6pOI1lf6kGbffAJCeDCpC0Eju69gofH5FhR+dcJ5xJgP4kA+IHqIjQi9AWC6UBdKeULICjxS/dOUL3x1V+ydzbVuaYX57fOlSSHdPB6Agi7hFXvctT59ehPecbmHDNqnFGtSgtb7v64f1tRoW8zvEmzBLvlilrMKYqCwWvIciQw3Cd/YrrmrQMcr7+jztneiBJIAADwQAAHAnAABwB6ko8vWGTQAumTlNYPnjh+s+YdF9DsP6hnefRN6Q6SeA/6g+zY0onQA/cxuQ0yFAEtlRlojAXavgDsT/J7MCG5S59ln8bpGlKUJa1zpRfQltcSoGzScCFzerL42AmvcxyeyaM02GzNjRuKiSeWeVSvBA1j6svHFHTjNry+p0ueJJ5HGXIAhnplfcrCDDhkumGrzBcVzRlkVn28vhber1+65439chlvSPNtplQVazGn17iJ3FqudLslkskxpd92kBzA6LKJUJwrRxXlTp9FNSWUlcpnxf5MZe7nEm3FItTjl51tUSMiFmPQZNVNpnWezTpiJNZmZLRKnightEA6JO07SUo2urNWz6+f0JCU1O/ztd+4F1GQb06WWfj/VlfcRpWYdu1aVX0RBUGSAb9wYsOQe9Eal7B7SLNZUglACxCAH+V5X4eG7tkvVx9JUYJgYw9OFMaL0yZFBG9wcD98YF4kIA73XflApXJmEZZAQCER3928uXhH+pr9hBALYBvD9VENIJGpS3rYni9p4VZ2D0zQhxquatVoWX9rfBIOjo1sykO7P62rZt8i3jyPxkxL72bCounterZQD16HpnQ07mho0s9Okjff/Jm6+9hZsvMUTOwlMyf5ffFX6rbiSKPrj1o3dmzJnTqlU59DswV5LZnnWWTlbH7yFQb3HWYdOjoT9Z8VozXuNd3fyg/NZsIC446gBnfFop1GnVVnbt1ilk+BGD2wZ5EuQvPhkPXUmSzONLtTzppN53515yFEmXVJDCs7O+rq6uqqZ0hRh1brnWpQA2CvTPTdmH4FbMe3T+UX43RgKrVpf+yzgM5ug7099ccD94hZB9mbZ9oaBL1+Sm8Nn6Dz3GZH/q8FRQzZcuP1f3meks6l+Pi4c63FyhU5E2FUC6evbi1s18Cz2zxMz/l4+PDyeft2/0SEUtm5M5fHuhG9k4sRAAM+OCTCB6/tFUFlmCwU2PhacvrSqWed54tyI2YpjfC5S0uohThKN3+9QKBxsUfrXap66/P/v3d2npcyjTtTb1LnoOEoxZVksosz4LDfMrUzOXM5OnYDfrPPGOULHaqGD1NXPsp2kp3OBXZhWtSPhNhtRFvSkE3F8R06bRvhMenURgbUcJWXOA/EyXaKrW1tq6urq6+vq6uqqa4zJavGIcr5UVKIV1PH3COya0rqL8vPzpRgJ0hcvxrJz3hu2XAftTng2i7rXCADpEWuPGDMQRYdaGdwS9cGrkCRNeOk8OSWCxhDhEn5+nvD6WwryNqnzrhYqBuXyv+H11P/Xk5PT88/NNN9px5c5f0KahBU6YtPL7f4NPS/xIxQzG/qp+8nXNT9M/f17N39qyd6rPfBz7/Co4dhCgAIYAvWHRkIBDdhViQkFBTd58/YoU07GzZ8lnBMYXtWr1+3YsGFRUUEnTZrEB0cXLPvE8y2YtG27RnytXq0bOnj2baTSF8GTLli3osniXSkaNGvXs2TPbtm3TRx99hIaGhnrNS/HUU0/FyJEjA2sFbIsQFYsWFAzZ86sWrWqePHiDRs2bIxnn30mGTNmSJGGDRtwvHg3a9dumR133CFXX311ZcsEFn4AYuOBj8fV3WRaFwAZQPCl644QWI/+YfEYgFa1bt3Z79+7p1KlTe/bsEVcuXEjl5eaW7u1VCoXlzjvvjLZt2/K9730Pe3t7UlNTU9WrV2teuXKSTJ68eEGsrFq1sHTp0pYqKurq6urq6ulUgkWLFqVp06YpLy+P/v379cILL6RIkSJfeOGFp58HN5bG0lmsFnt28bF0NAQhp4PY2Mj/mAzpw5sxGrVq2sf/++pkwZMlSICMju7cXypQp0YIFC1ZsxZIlS6xbt66cfvqpKiopL7/8gsPDw6aefLo+/e1uWLVtGr169lZubq/Xq1UpNTc13v/nNy8vL1apVJ0lAFDgA0Xr5cLFy6skydP1tlnnzV9+w+w7s6dO9+63v2269Uro6OjRnDhxoqZmRnoM4sI1awyo6fr1q2b9evX69atm2TQoEF87rnnct9997l16/M0bN+rb3/42d/fKnz/9tdWr12bJEnU1NSkbNmyttxzS772t7/l0UcfTa9evel5550zZ86kuLg4M2fOzJ07t6ZDhtAwQY5dFhQUUMHfftUi646Cz2+zMU3PdKPO0f2fe0033yz//Oc/2rZtW4sWLap69eqcfv26Oj4+Nib+oHABLEuGUCg2bNkaNGpWNGzdu0aJF039//7oHH3zA7bffXtttt10XXnxRq1at0to2UlJSYL2/33vf/ZRLb7vU4cePY7RokWLGDMmDM2aNUNUVFTQpk2bFs86dOyYbm5uevfdd2WmpqZRfh7sIiMQ4lGo5+aNv3bo1LrzwwsbMzPRbqKDgb38EPDjGetCrakWmSkpJs27ZN5sGDB9euXTud509JamqqRo0aZcY//vgAq1evTs2cOUOzZs2VKNSoULDyr+bMf/1r33ntvqlFisWJFvV6vl6FDh5b8+fOpUBBARo0aZbF//37nzp1TK1WiycflVVdclr0d+5pV6/v9Elf/wwNfWnT59W0NCQK17++ee9fv26pUuX5qSTTpIk3bt3sfDgQRUYGJiwYMGCD1+/xixZsrCwU2FhIVq+fLmr1+/nscff5zk5GRdevWqFg4cKCCwL4dq2bN2vJkydv27Zty4cKFfr9731927d+//vf/+XNN9/URL5/+1pqUgIZNmzYwZcoUu+66S9deeqmmpkaHDh2al5eXrFixIm3btqXp06epqaWVMm3atGWLFmmyZKnWr1+fH//4x94+fXrbsmVLWrBgwdixY0fq1auXUq1Wq3LlyrVr1y51e75vXr1/VqtWrVaPSmjXrl3atGnT5eXl5enTpyubNm2qYcOGqqOjU2dlZGxtbXVmzZqpZcuWav78fWrXrl1NmjSJ3bt3lkqlUgmGDRvs2bNHi0XU1MTmzdvVq9enZdeeqlGjRqlUqVKhw0hxowZNHFihVZtGhRLVrsgs3ZQJElS1bNL/99lvVqlVZtmxZVk9PT2H04MCAlS5YUMaPH4/rr7968+fPq7CwsFqtWpk5c2bcuXNj3rx5Zs2aNZ0+eVKoUCF23313S5IkoUOH2rBhg7Vr1y62bNmi2LFjx5ovlfLp0yffvn27f//9auXKlQoULKjRokUHBwcaJRo1YociTh48fLxo0b584777xTrFy5Ujo6Os6cOSMiIiIWLFiQ2LFj69dv16tXKz/BYbkb327NhRaWmpSpdu3ZVyZIlL168KNChQ1q4cKH3v//9OfHEE9e0adN27drl2LFj2rZtW1q1aqXa2tqqWrVqkyZNiolS5Zk2bJl9e7dW8+ePR06dKhdu3b10EMP1du3b/z4xS9UmzZtUhYuXFh06dKDiscussUn6ELFy45f/48x44d87Of/WwqKirq6tXLly2VfWAlzFmzmzdubNm3SVuwAkP09Tx8IrVr1+Zn/q//fbbb2u0aNEmNzfXT37yk3T99dcrKytLeXl5OnbsWL169UrNmzdLTU1Nn7uvYmIiDh48mLdunUpNTdX48ePT913311de2bdtWixYtalWrVpt375dedlpuWp6eWk2bNrVs2TKtWbNmzZo1de9857XXXlu1atWaN2966qprVq6sr27evFf8kydPzvLly2vTpk2TOXPmrF+/Pq6//nosnRHLzZu3qtWrVq1evWq5s6dq6666qqFBQUOD27dvFmDFj5emnn66goECbN2/OokWLWbRoUcycOTMHLFjA++++2zduzYVKNGjUpLy6VdevXqampq6t27t+rUqWPCBIPBERIS+s///vcsWbKkaNGiKhcquHBhw2jZsiVbtmyppKQkK1euTE5OVoaNGvWJJ54oKyurhoaGKioo0GpVw4cL0+fNLlx48bJ++zZs2atWrWq3bt2rVbt24NGTAgsbGxatSoUfr27Ruz2bNn9evXr+jp6bVt24bUqVPLny+vAwcO1KBBg2ratKm4uFh9+/apU6cenTp1irZt2/To0SOpX79+dOjQIfmzZ8+YMYNWrFw5cnt7m1auXOnQoUNF2FhYvPLKK9W2bVt//vnnWrduXUOGDEnXrl1Tr149pUuXbli1atXWrFm2bt2q6tWrYsSERYuW1KWXXkpJSUlJS0srqaurZs2apUuXKisr03///WcdOnSQKVOm6tWr16FDhxRzc3NefPmpXDhwtZbb71Fb775RlOnTuWCCy6QKVOm6tWr16FDhxQWFiYXX3wx1apVq9myZWvWrElSUlKqXr2qUaNGqeXKlZMkqaioiMXFxXz88cfy8ssvN2PGjImNjXV99dW5a9euOnfu3Pz4xz/KyMjQixcv0tKSKDExUdJkyZK2LFjmzdvzvLly9O9e3eA5W9/f3d3d3133/bs2fXz8+PHj9922y1nz54dRo8enY2NjaRJk4ZlyZJl1apVlSpXmzVrhgwZoquuuddcsQQbW2tbbRp0/IqKipOnjp1ysvLS81MTMCcOXNiYmKCg4NDWrduTUpKSpqbm7Nr1y61bt1aLly4oIyMTRs2LM2YMUNwcLBLly+Xjh07NGnSJCNGjMg999yTetdCw8PDlStXplu3bgwZM+Zo6dKla9eu1atXr6TatGmLZMqUKVWevHkly5Ytk02bNnV48WLmzJmjt956K+3atUtVq1bl6rVr1atXkypVKqpatSo9e/ZMbGxsSk1N1erVK5kwYUJevXqlEydOxMTERG3evFlPPvlkkydP1jBhwqj79++TjIyM0LhxY3Xr1m3atKm4uDg9e/ZUhQsX0pEjR2rVqlWbOnUq29vbo06dOqW1tTUmT56s7ty5lS1bVtGiRbVq1crKlStfueUReGrUKhcvXuTIkSO1bdtW9+7dY8aMSTt375bVqlVlypQp1a1bolmzZmnWrFkNdxaQ/v37GzNmjM6dO2eTJk3S5MmTWrdu3fanU6dOWbbxjmlKtVt26dZGQkhQsX0oABA2bNmpU27Zt05lnn60aNWrmzp1bTz/9ZIvLYSuXLl2qWbNmAN9//30tWrRIp0+fVuPGjUlNTU05cOBQbN26tXr16tWLFilqVLl+rdunVSsGBBd1122+a///4r27ZtU3Nzs3jx4jR582ptb29bunTp1e9e/WcMGFC/POf/3SZzMnJYOUm07dNkmNGjWq0KFDsmrVyuiRIzV8+HCtWrXSy+11HHOMATE1NZUxY0by8vJ85stFkUceyXvvvS+iRYtq4sSJtm3bliTJWrFiRba2tnRp0+pUKhX33HNPli1b1qqn7dq1S5Ikn376qa1bt7Zly5alc+fO6tWrV9OmTZt06tSpysqKCllZWaWkpETTp0/PmDFjlixZkm233Tp+/Hjx9OlL3+Zd955J2277TakpKTUli1bsuWVV9iuXTv19ddfXXzxxTnvvPNm169f169fT0tLC378+I0bNyYmJsZGq1evzqabbmqFBg2qcuVKb7zxRmPHji11/vz5GzZsqMPPHAAamtrtfv2ba2bt2a9evXq1KlSgYMH6/e///1av369O3bs0HHHlGHDhuWxxx7zrW99q729vWq69eunsWPHJlmyZKUkJASTyQiJ0iRJ9O/fv8aOHatRo0Zav/+/Zp+eXn56aef1tKlS9O4cWM7d+5MEydOKBQK5eGDBxdu3LB69erZtWtXxYsX1zPPPJOcnCw7duzQ1FNPpXfv3lWrVrX17Nmzr5tuvX89Ro4cUJs2bSosuXr3a0qWL9eDBg1q9erVWrlypZs2apuXLl5eeeqrVr18br776qomiRYty2WWWqVatWrVr19q9e7du3bqleaNGielSfCIVOTIkRUrVqR06dJlypQpPvroozn//PNNWrZsqVfV1NRUyc3Npaam6upqU1NT06effrpmzZqlZcuWaWpra6qqqlOmTElOTiZJkpOT06dPn+rdu3dJoEHBwdrbm5uUlBQQF999VX7+9//vhUrVqRp06YVK1Zk//33zxadOnXu3LmTJGVlZbr55puam5vr1q2ryJEjOe2009exZ88+cuihh9SxY0eTJ0/WuXNnqV+/fus0btyo4OBgie33S5ddcov0uXLm266aZ2yy233Pjhhx+080477ghQUFQuX758WrJkqcCBB3r55Zd1+vTptGvXTvPmzSVJUk1NTUpMTExER0fTpUtn2LBhqlGjRqnChAlbt26lePHidddpUyZIlBQUFadOmjZo5c6Y2b95siRMnNHTtWs8ePdTgULO1bt2auXPnCoWCzp07d263b9/LysqyoIAAu9du1YABA3Tli1fq8GDB9u3b5+ioqKpezZs9WrV6+SJGP4sKLdu3eratGlTWq2amZnn31WCwwMZcKBe41mzpzp0qXLli1r2bJlBwcHK0mSJH3ux8yYMUNUVFQMHjyYCy+8UFu2bEmaNausH3oOHixatGjRuHChQu1eu1adsONGi06tWrFERMTk5+enu7t5s7d672FD58+SJGjRqlUKBAZ86cmTp16uQzZsxQXFycc845Ozo6Gizc+PHjarXr1u0OQAiQULFhQePXqkl5dXWrZsmSoqKkpLS2vDhg37+/dPlUqlUtW7dqtWrV5uvuXLlyiU7d+4cl2wkg3h20adM6d+7ssccemzVrVoUFC9eZM2e66aabmjBhQgwfPpz/+9//9fu3b7dq1Sps3rrZtWuXaty/XyclJkyZNEjbdu3e3f//99+8/mz59fuDgYKVGjorCwsFavXp120yklUBYfS0tLu3btloYceKmtrW06fPs1jjz2iuLg4P/roI/M/P5cLFy7okw8++OBe9+uuvWrZs2XbhwIS2bdtUUlJiYmIioqKioiKbNm2aJElduHAhZcuW1b59exw8eJA//vGPW7ZsWV6+fKnx2M469ehRiYuLWr9+vXbt2mXJki2rTpk3y8ssvBQUFauzYsXriiy/q06dPhw0bFxo0aFCeffbZ7t27x2GHHZYFCxYszZo1U2BDs2fPtt122xg6dCh7d+64ceMiIiJSLBaLHGpsbMwVV1wRK1asUFZWlmXLllX8Mf4uLiZM2dOdevWjeXl5c6cOXPr1q3Tpk1bt25tc+fOVZcuXaqYmCh48eLJzMzMVKpUqZIvX56VK1dOJ09enVitWjXrrLNOK1asMGHCBBs3bsx8881TW1urevXqlS/fvimxsbFgwYEBgwYN2rBhw7Zv3z4tWrRI2traOjo60adesWbNmTXr48EG/fv1q2LCjRYvUq1dv2LBhxowZG2vXruuGBgY0Y0bNyYmJiQNHTrkaNPG9evWqVatWlSRJN2rUKCKj/QMWLWq9enWKjo7Wq1ev1atXW3p6uozwrNGjR2fOnFHevn2rq1atKioqSuXPns37duroaFBd+7caRB74MCB1atXFxwcnn766Zk1a1atWrUqXn/9dbr77rt27d0+WLl1acHBQmjBhQtbW1pRZWRkVKlQwvLw84+PDo3769WrRowb777/t/r06Xrs2LEFCxYUKVOmRFFRUb377rurr787d+Tk9F9992lTp2bVqlW5++67atSokZGR+vXrF5MnTyoqKhIoUKFkydPtuuvv3Tq1Clnz55NkiTp3LlzioqK9OrVqzVp0iQNDQ1SaWmpXnzxxRQUFJSam7uxPb22r9/P0OGDOnbt6+0adP65je68MIL9e3bN1OmTKmOjo4qKipKDhw4qFDhyo2b95s5cqVWrRokT1799apUuX07Rp0wrNsHNzU15eXmXLliXp06enTp0+rbt06WrBggX7yk586ePCKioogPbbbuN2267TS9fvmzJkiWrUCqVgtZ9++qnScz1VV1zRMzz8XE1NTc6ePSuLi4uDeqtVVV3Xy5EnVrVuXf/zxb169urdPnTp++OGH9erVK9WqVampqRUlJSUHHnrootWrV1NTU7Vt2zZt2rSJEycmJsbmzZv169fT1tbGxsWLMnj2bOXPmqVatWjo6mmuu2Z/ftWrVSkuWLKmnnhpqampqaWn58s1a9ZMnjw5NTU1GR4e7q9Wq1mbNm06cOaNUq1bpu+++y1FHHZXSpUszceJEpkyZkiRPrl276ti1axdDU1OSc889F7du3j//+883b95cdevWVZM09mnDEVG/crAO0WYY+CZgPshIAAKJtErVq1a8aOHZtTTjmlmzZt0mzZsrg8CFq1apVWrlypq6qrFixordu3VLNmjX1yCOPZPTs2dNZs2aVJKX8GBBYsWKFawYOEhmz59tmTJko7y5ctXrlxRbGxskJUuWLH9QDabMmbHDhgU1e/bsVK9enU2bNq0CAwOF/fu3Tp06FBhYWEJDQ1OkaNGGTRokVatmyZkpLSibs7G9WpVauceeYZaWlpIo0cP169fT3l5eSbNmjU1e/xobW3ds2fPxpEjR/T09MyZM6eTJk2qd+/eWbFihYULF17ylzu0adOKhQIUlJSUUFRWlrKzM8+bN5dChQ2XLllWbDRs2rFUrV2aSJUvS1q1bhw4dUih/jjatWrXq1FdffXXOnj3b/PnzSzvC5IeggkKSJAwoesupVN33qpdmzZ15syZU6FDh9aTJ09UKfhwYN67dq15333tZWVlamZmZqamoeffRRrVu3Ts2bN0+lS5fqd+/eqVWrVrm5uaenp7Vr1y7WrFlTI0eOUNu2bWmhhtZ4/fXXdfTRR1K5cmV98sknurevX3n66adUz549mTZtWj777DMteeWVVrVq1aqxY0dq2LBh3bp1a3Tt2tUSG6WL2rVrl/Tp05ednTJVy9etF544YWuuOKK1qxZE93e3prfetd9+/btsmXLtmzZMnbt2uXdd9/t375diRMn1tzcnLx582rHjx+2bdvWkSNHZsyYsVZF3HnVZs0a9ePeuedddZvIQxVoVAfHz87fv38avyV3d3dJGfRoUe3YsUNZvXp1ury8NG7cWO666y6dO3eujz32yHPHjk1NTVWKFSsiIiJOfvkll19anTp1AgwYUPTo0QOIiIiXL18OuVydd9xxvPDCC6tZs2YnT56sBx54oOp2eFRCJPbee2/PPffMnp1epobm0uaNElwcDB79uxhaWmpioqKWrduXf7+/ioqKmpubtm/fHp3d3d3Vp0yZ3bt3T3d/ftWqVampqXr16qU0335xz585t3bhRY2Njampqqr///pvLLrvMuHHjNG3a1Fnz58WLF6su21333Xf17t1blixZou233+qBBx5o586dWrRo0Zp9+3YrR44sS5YsycyZM6deurnt1+9dtWrVqtWrVurZs2aWnTpqW5uTmFhYaYMGFCYsWKFRYvXpwZM2Zk0KBBwr17986cOaM9e/bkbNmyfrsBHTlyxDh/YsUJ4C7NmzZrRoUM6fPw8nTpzocHt7a+7cudoFCxawGDhwxpAhQ1z951I0aMegqKpL29fQyYMCA/P39zM/PV3p6urVqtdKmTTv77LNjxow5/PDDamlp06ZNy6JFi/wXhgYGKioqunfvXoMHD85uc/ihhx5Sv3791b9/P2vWrFGnTp06c+YMGzduTG3atOlkMjLSrFmzppUrV8qUKVOUmeF6yZIlFsOGDbVq1SpJyclCfPHFMzMzWbpmkphYyYwZZLPZFk2a5EMP/hC+ffvqnDlz6tWrF7R27Vq33XZbNm7cuJJp06Z12LBhlixZklmzZhU9dDQ1NTXJGDs7J/kcvHhxUbat20bffr06Xz55Zfn8ePH33333Zk3b96ampqquTZs2aRJk3L27FlqtWrV1apV0xRRESsu5cKFaWlqqevXqcWVxfsjYsGM9+OCDegyH76FDh9i9ezebN2/G8uXLbN++fcXFxWrXrl3i4+OdOnWyYcOG+vbteurWrUrXrl11vcbGxiRJk9SsWTPOOCMmT54so0aNyrJlynR69WqmfsvF+fLlNWrUqNG3aFB83exHr1dglSxatz51FcnJyWLNmTSZmZGReffVRzz//3F+1atWSJGNjY4b1799fjjz+ued1fvXrp/j4WFpaKrdu3a1bq1atJUlJSWbMmFF+/fplzpw5qqOjIxts3Lhx2bBhQ27evFmHH35Y165dU/LkiU1NTVq0aFFRUREZGhlz5oyNGjWqvLw8ufnmm3rmmWeMGzcup0+fXgMHDqzdu3dFsbGx9evXr+/evXfnllWvXrl23b9+uVatWxYoVK9S4cWNWL14sc3NzVq1dvp0aNGpaamqlGjhuLv769evWrZsmZUvX661b99uxowZrfr06ZsyZUp9+/bN+vXrdnZ2iquuuvmzp06Wltb29SpU+fIlSsXLlwoLy+v93czZsyo3WtxnHBa9IBddZyFdOXKlVaupdsEyPElfetWvX5eabb46zs7Nqt264fft28eHD6dOnp0cffZSuXLliYmKiaNGmyffv21aqoqCAoKClpaWta3bysra2tWLBgs2bNkti1a9eMHj26cuWMK1eu1O7du82cOVMaNGhQn376KY0bN6Z///5bjz/+eK1uyuWXn3xyS/PmzZO777476tWrF+uUkJEKFSswd+7cNG7c+NG9e3c+PLKK9euXTvRpk2b1KiRpk+fnjfddBOWlpbGihUrZs+enZEjR45Mz81W5cqVavXq1d2wL49EgtFcvX1bo0KFOnjxZYmJiZNKkSSZNmlTWrl2bZcuW+vp677//vp6eHnV1dbVr14YNGhQLFixYsONHtGiRLFu2jVr1qwrOwGHDrjxxhudP389w4cPp0uXLo0aNJSEGhpliRMn1qZNm69997717tlz587t0KFDOnbsmIaGBpWUlCTbb789mzdvTpJk7NixauDAgSk1NZWmpqrddtttdOjQIW3aNCmVSsm2efnmzZv3++moqIhed1HRkYqPz+fww8/nP3790+PrK2tjffr1/convertpbZs2ZD27dtbYGCgoKj8WbNmaloqCgf369fv9Xiya1sWDBgrVr10Y8//tjWmQAAAACwpACAUAAA/F1oTcAUAABwJnYAwKXuHR4eqq+vj1Wrt2rU5c+ZUV1fn5Zdf7tixow03btyoZcuW5ZVXbnXVrVs3hoaGkp6errJly1Z9+/Zt2bJlus9hORkZaW5uLksWLUpLSxNLly5ptqiYgJk6dGjp37uys2tvbatJksbGx6tep0+fPlIyM1O/vz/Pnz3dmzZzU0NNTR0VV5eTlOnDijp0+fZvXq1Y2NjWXLlmXxrmXLlinYuHHLkyNH+/fsrVqzYmjVrqly5csV1fjw8XrVq1drkzZt1+vRp69fvvHbbi1DdSMoksenTptW0adOvX7/e3Nzk5eVp9+7dtGnTxqlTp1aDBg3SePHioV69e9euXbsyY8ZM3bp1q1GjRrVr1y56e3tTUVGRf/DBB4qLi933t7yHDx9eJCSSUn379i2tra0aMGCAarXr19asWPFCz/60QeyZcsmIyMDXn31VWfPnk307lzJL37xi0aPHq06d+4sSUlJkaSRRx69ZMmSOXPm1Bw5spQsWbJ69eqZMGGC//jHP0xPT+/VrVtVq1btiRMn1qpVC6lUKHDhw+tXr16JFi3qFpa9e7cWLlyoP/906dPjx49KioqYuDAgUmTJmXKlCmDAwN47733enp6OlhYWOlevXooX768srOzV1x498rKSu3atVPTp00bNzZ06FAlS5Zk+fLlNGjQIM2cOYOGDRsUK9euzZ07l+TkZL1793Zjx44tXrxYli5dUqNGjVqlOnXqdOnXq1KnTTjtt3bp1NHbsWFOnTq2yZct2goODVV9fnzVr1+qBBx7Qrl27kiRbtmwoLi5WVFaWBg4cKK9evampqapRoxZp1apVJ06cUKuWLaumTZuMGDEi1apVtWrVqpUrV4rfvn0NGzatGm3a1AlDZV2551366qrrtChQ7Vu3TriF7/4RZ06dUqfPn3qeKcaNGiQDRs2VEJCgpiYGKGlpaXOnz+vXr16YcKEgQMHdvz4cT799FN16tQpIyNDLa1eXb9+vU1a9YsyZIlmUwmTZYULFjQ/fffF1VVVaurV68qIyNjTz31VCNGjKjChQunp6dTpkzR/Pnz27dvT6WlpZo2bVqeeeYZu3bty888/q2rWLQ8++KDZ2Vnz5s2raNGiDB8+vEyZMqWcnJzU7NmztWnTBggULBwcHK1euVI0aNdK0aVPkyJEjqamp8+fPb+fOnXLu3TtlZWSk3XHHHbr11lu1bt06Ojf98z//U69evXr4U7/61V61atm4fPkyz5s3VxYWFhYWFmpra2u3bt2+tra1btmxRTz75pJRUlLCwMJCQkFBUVJTk5mTVrVkOGDhWaNWvSmjVrLq2ePXu0ePHiodLS0nYwndrapaWlnz00UelbNmyfrOvcM0117BcI0OLhpJXq1bro6GHz5s2L5OVLRo4dq92LFCt122y2fPn2yYcOGVK9eXUOGDm1atUq9evUqQ0NDW258/HxaW1urfv26uXZsGZk2bUro0aNff/0dr1e//evXX385AwcOlC222iqffPKJz372s0OGDRs0bdp0kiQbNmzQ1NTE8ePHq2bNm7Vr1ypWrFiR2LFjlUqlEsOGDcuyZct06tQpq6urpaWlKhUK3W7HOTk5lS9fXsOGDaurV681UqlUPvbYY3Xsscc6s2bNVq1alZcvXpRff/2l2rVrsvLyzJ49O5s3b66GDBmioxYtokmTJrVt27ayZct06NChxowZk6VLl7R79+71+vUrq1at1dPTe++9F79131hyZIlVauWVdOmTYsTJ06ouLg4IyMjpp2dHampqaXLl1UoYGNja2WLVtq/vz5Tp8+raFDh5SKFSv06tWr8+fP57Jly6pXr5ZNmzZQv359K1tba6WlpX1m+fLl6tSpI0OGDuWll14iIyMTHh6em666aV155ZW2bNkikhQq1XJlzx0/v9/y5csraWmptWvXvhMnTorI0dGRlStXrkpPT6+0+rVrZ86cUK9ePRwdHaXr1y9Zs2alp6dLzD6VpptsycL4JqcpIEg1blzZ0mSJEm0adNGiRMnelalVq3atJf9/f2VM2dO67777gQYMGKlCggF+/fnX99dfr8uXLs3DhQldffTUqlUqlTZs2qXnz5/Pnz2/OnDmazp07uvLKK4qMjOTMmVN58cUXNm7cqNWrV2WsWLEiIyODCobG1tGjRqlT5+uFCpUoUOHSmjRoosX74c1a9fp8OHDauHChZo6dWqsWbPKycnR2bNny+WXX1Zqampm2bJl1apVq9q0acv0xx9/3CGHHaXixYmTJk3Sv//+K6VLl/Jrr71m9erVuvjii1SlSpi5cmXdeeed9enTlw8bNoxMGDBA8+bNF1dXVrBggUNGrUK9erVS5MmTbq+/fr69NNP68OHD1u/fn2tWrXK6KKLlSpVcmTJks8//zzGjRqlcOHCK1YsUJ9fXtKSkqiqKgoIiMTk1ntuXLfeeKJPa9asqZUrV7R8+XI1a9Z8+eWXd3t7q2299ZYGDhxY8+bNywsXLioTJkzIwsJC62zUmDEMGTJMlStXeumll0o//ehjKisrS5IkybRpU2r06FFOnTrFsmXL1Lx58/pi0aKFGD58uDh06FBsbG5arVapXbNmyTp06tRkaGmppaXHdddeRLbfdfvvta9GiRTWrV6+6d+8eF110Ufr16+e0ZswYzZs3T0lJSZKeesop+rpa5969dprrqmu7reMRWLMzEx9fX128sknuvXVV/r48aPq1avnrLPOqly5cpYvX07///7b5MmT1a1b1xUvMvLkyXr99dd16tR1W/E2aWmp58+fX+vWrXO0sLCwUG5uroODA4ULF962beiLFK9ePXLlyqr//vvr5MmTWrFiRV133VXWrFixZMmSBAkJya1bt9bQ0KBLLrvsZcuWBez+fUqUKEGbNm23dOjQBAoaaXHlxZMgQdtt992rSpUtau3atpk+fnlrZsmWLFixYWlpaioqKlSpVUri4+NToMAB2rBhg543YMCAXnrppXnz5m3FixeroqICfHw8h4eHuru7a1mzZmpqapMvPDyccMIJb9++Xf3795WUlKS0tLS/v5+ioqK1atXl3nz5klJSk4fP66qVSqmp6erX78+hQsXtuGCBW1YcKBiYibWrFmznTt3l06dOlXGxkYmJiZe+65J+PGjdP8+fNp0aJF+vXro2bNm1qtWrWFCxfWP//4w5YsWZKkpCSVFhZqe3ubkZGRbt++XZ07d1auXAmyZEkNjo6ukydPZv169crIyEhJmTZtEhUVFcXExAwy6vn27zZo1U7JkSaxfv17HH388W7RoUeWlpS5fvpxrr72m1atXP/vZz7Rp0wbr162TSqVRowYICZs6cqZUrV7R06UrNmzdTJ05ckUdHR1myZElWr16dGzdu2NTX17Rp08ZTp0ypVq2aW2+9tUh4BPn5+ZoyZUpoqKiknTp1opWrl5qeHiYlJQUvvnmm9WrV696zQ98T4vFkydP2rBhg+7du1etWrXkzJmztGnTSlkZGRycHCgoKO3YsUNPA/mPPveYW7du1cE70LH16tXt27dPTk5m5qamZT3O/b7u7evVq5cmXXrl3TVq1eFUuWLHnz5m8HH3yQJPm1iUYHBxosWLChQ4cqNjj1dTUqClTptS5c6eqWLGiBh07dkxOTiY1NZWIiAhNmjQpkydPauDAgdWoUSN33nkn8+bNS6+//kqSpKSk3333XYODg7VmzdplStX5s+fl3Z2dmZmZmptbY2DBo0qHfv3po+fboBAwYwYMAAChcuyPvvv1/HHXfs1FNPTzMxMZi1axfr1q2rdevWFi1aVKOjo4qLi1NPJkYMGTI0KMvLSwYMHZb+/fzNmzJjWrl3bU089JZJcL5r0lJQUeuKJJ7R3717nnXfu0WGFChXUqlWr2b59u4YMGUKfPn1CoUOHxowZk7p16+rQoUPy8fGHCgsLX/jCFwwePLhWr16t9PR0rFu3rk2ePCk9fX2opKSkI0cOpU6dOs2cOZO2bdtKzMzMtGjR4vh4WFVVVVl+vTpmTlzptbW1rr33WmGDRu04YUXyopKaKOHTsGrhg2bFhp06bFpEmTzJ4+3dKlSwbvHtNtbW1aWnp+svfbfdd1/VqlWT0aNH16tWrX7961VX7cOGCCgoKYsWKFfr06ZP1/e9/f6VLl1avXs317t2bSZIOjo6trZ2Uj8/34J8b4tStWrVWrVqlL73uc/3zz001157bb333stNN92UNDQ0WrZsqW699da1a9dOS0tLF110kQkTJqR///5be3t7kpSUFD377LP1140bbL/N+Zg0aZIkf/zjg4mISF77rmvt2rVL/v4ddtghubl57LHHcvLJJ9e8eXOxzZ07N248eakti5Yt1apVq+Xz+QoTde/evbrpppuyZcnSWbNmVVWVm63bdvWZZ5656KGHSZJMmDCBOXPmtWvXrl69ukqlWqlyZcuqXr26q06dP69atW0OGDunTTz+pbt06rVq1UtOmTavcT92amprs2bN7tGjR0uWLNk4cWLPPfdcU6dOXf3+/enXr79ChQnT06FH169dn4cKFq6ZNm5KUlBRTU1MyYMCAhISEhQsX1qeffpoJEyay3338HNPopp57ayNGizJ49u4GDBiQhISEWL9+fZkyZUp3nO+BBx7QqFdftG3bNv369UrNmze3du1a1qxZ07p1az755JPFixdr/vz5zJ49q+GDB6vNq655prq1atX4ODgOnXq1B333FFBQUHT+q40aNH6+GHH5ZeXr40ZMyoU6dOpaamqowZM/IqKirq1KlTODc4ceKo+fPrVq1Uo++++qVK1d2yUmTLFmyPCw8pSMHNmzYsBdffHHGjRvr8ODAaseOHZDSokX1iSeeqFq1am3btqlKlSqzZs264IILLtCwYUMaNGiQvr6+li5dmkGDBqlw4UBLly6pa6urLr/8srFmzRo0bF1WVE2LFim3cuHFq1qplzZo1rl27XnLkyNG5c2dq1apVGjZsqFdffTXt2rXNnTtXZ2dnWrVqFYsWLUrPz8/7+vWrnTp1ouDBg2tXr56mTZtKkiRruXPnztKlC/Pnz8+GDh2qcOHGoRowYNWo0mTpwpI0eOyFelUurka9eu3bx5Uz169MjKyoq5ubn0799fr776amjZtiuHDh9euXTuyZcuaP3+eHw8PWr+/vmPGjGl37lzjx48ratOmzZo1q6ampsbZsmVVqlQpSbIsFvjb+fPnWbt27Z599pm1btu2bdo0gYPHgypq6srZcuWVb744gvGjx+vU6dONYMGDefOnbt379bbrnmljRs3ruDBg7Vr1y4rV64sbGxsyctdff32mtpdeemlt378fzZs3U6dOHauXKlVq7dm3GjRtn06ZNioqKmTZtWnRZs2bl0qVLOnDgQENDA1avXk3PPPM

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E–11

8. Circuit protection

Balanced generator and load devices complying with this Recommendation shall not be damaged under the following conditions:

1. generator open circuit;
2. short-circuit between the conductors of the interconnecting cable;
3. short-circuit between either or both conductors and point C and C'.

The above faults 2) and 3) might cause power dissipation in the interchange circuit devices to approach the maximum power dissipation that may be tolerable by a typical integrated circuit (IC) package. The user is therefore cautioned that where multiple generators and receivers are implemented in a single IC package, only one such fault per package might be tolerable at any one time without damage occurring.

The user is also cautioned that the generator and receiver devices complying with this Recommendation might be damaged by spurious voltages applied between their input or output points and points C and C' (Figure 2/V.11). In those applications where the interconnecting cable may be inadvertently connected to other circuits, or where it may be exposed to a severe electromagnetic environment, protection should be employed.

9. Detection of generator power-off or circuit failure

Certain applications require detection of various fault conditions in the interchange circuits, e.g.:

1. generator in power-off condition;
2. receiver not interconnected with a generator;
3. open-circuited interconnecting cable;
4. short-circuited interconnecting cable;
5. input signal to the load remaining within the transition region (± 300 millivolts) for an abnormal period of time.

When detection of one or more fault conditions is required by specific applications, additional provisions are required in the load and the following items must be determined:

• a) which interchange circuits require fault detection;
• b) what faults must be detected;
• c) what action must be taken when a fault is detected, e.g. which binary state must the receiver assume?

The method of detection of fault conditions is application-dependent and is therefore not further specified.

ANNEX I

(to Recommendation V.11)

Cable and terminations

No electrical characteristics of the interconnecting cable are specified in this Recommendation. Guidance is given herein concerning operational constraints imposed by the length, balance and terminating resistance of the cable.

1. Cable

Over the length of the cable, the two conductors should have essentially the same values of:

1. capacitance to ground;
2. longitudinal resistance and inductance;
3. coupling to adjacent cables and circuits.

VOLUME VIII.1 — Rec. V.11

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Page 107

Cable Length

The maximum permissible length of cable separating the generator and the load in a point-to-point application is a function of the data signalling rate. It is further influenced by the tolerable signal distortion and the environmental constraints such as ground potential difference and longitudinal noise. Increasing the distance between generator and load might increase the exposure to ground potential difference.

As an illustration of the above conditions, the curves of cable length versus data signalling rate in Figure 8/V.11 may be used for guidance.

These curves are based upon empirical data using twisted pair telephone cable (0.51 mm wire diameter) both unterminated and terminated in a 100 ohm resistive load. The cable length restrictions shown by the curves are based upon the following assumed signal quality requirements at the load:

1. Signal rise and fall time equal to, or less than, one-half the duration of the signal element;
2. A maximum voltage loss between generator and load of 6 dB.

At the higher signalling rates (see Figure 8/V.11) the sloping portion of the curves shows the cable length limitation established by the assumed signal rise and fall time requirements. The cable length has been arbitrarily limited to 1000 metres by the assumed maximum allowable loss of 6 dB.

These curves assume that the environmental limits specified in this Recommendation have been achieved. At the higher signalling rates these conditions are more difficult to attain due to cable imperfections and common-mode noise. Operation within the signalling rate and distance bounds of Figure 8/V.11 will usually ensure that distortion of the signal appearing at the receiver input will be acceptable. Many applications, however, can tolerate much greater levels of signal distortion and in these cases correspondingly greater cable lengths may be employed.

Data Signalling Rate	Cable Length
Curve 1: terminated interchange circuit
Curve 2: unterminated interchange circuit

Figure 8/V.11 - Data signalling rate vs cable length for balanced interchange circuit

VOLUME VIII - Rec. V.11

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E–13

Experience has shown that in many practical cases the operating distance at lower signalling rates may extend to several kilometres.

For synchronous transmission where the data and signal element timing are transmitted in opposite directions, the phase relationship between the two may need to be adjusted to ensure conformity with the relevant requirements of signal quality at the interchange point.

3. Cable termination

The use of a cable termination is optional and dependent on the specific application. At the higher signalling rates (above 200 kbit/s) or at any signalling rate where the cable propagation delay is of the order of half the signal element duration, a termination should be used to preserve the signal rise time and minimize reflections. The terminating impedance should match as closely as possible the cable characteristic impedance in the signal spectrum.

Generally, a resistance in the range of 100 to 150 ohms will be satisfactory, the higher values leading to lower power dissipation.

At the lower signalling rates, where distortion and rise-time are not critical, it may be desirable to omit the termination in order to minimize power dissipation in the generator.

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ANNEX 2

(to Recommendation V.11)

Compatibility with other interfaces

1. Compatibility of Recommendation V.10 and Recommendation V.11 interchange circuits in the same interface

The electrical characteristics of Recommendation V.11 are designed to allow the use of unbalanced (see Recommendation V.10) and balanced circuits within the same interface. For example, the balanced circuits may be used for data and timing whilst the unbalanced circuits may be used for associated control circuit functions.

2. Recommendation V.11 interworking with Recommendation V.10

The basic differential receiver specifications of Recommendations V.10 and V.11 are electrically identical. It is therefore possible to interconnect an equipment using Recommendation V.10 receivers and generators on one side of the interface with an equipment using Recommendation V.11 generators and receivers on the other side of the interface. Such interconnection would result in the interchange circuits according to Recommendation V.11 in one direction and interchange circuits according to Recommendation V.10 in the other direction. Where such interworking is contemplated, the following technical considerations must be taken into account:

2.1

Interconnecting cable lengths are limited by performance of the circuits working to the Recommendation V.10 side of the interface.

2.2

The optional cable termination resistance (ZT), if implemented, in the equipment using Recommendation V.11 must be removed.

3. Recommendation V.11 interworking with Recommendation V.35

Equipment having interchange circuits according to Recommendation V.11 is not intended for interworking with equipment having interchange circuits according to electrical characteristics of Recommendation V.35.

VOLUME VIII.1 — Rec. V.11

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ANNEX 3

(to Recommendation V.11)

Multipoint operation

It is considered that further study is required before parameters for this application can be precisely defined and this Annex, giving provisional figures, is intended as a guideline for this study.

1. General

The point-to-point interchange circuit arrangement of one generator and one load might be expanded to a multipoint arrangement by adding generators, receivers or both, at interchange points along the interconnecting cable, as shown in Figures 9/V.11 and 10/V.11.

Only one generator at a given time would present its differential voltage at its interchange point. All other generators would be isolated by an appropriate control, and assume the high impedance state defined below. All receivers would be continuously in an operating condition.

In multipoint configuration, one or more terminators might be required at the cable end or at interchange points, depending on the application. The combined load impedance presented to any active generator by other generators, receivers, cable and terminators, must not be less than 100 ohms.

The operation of a multipoint arrangement must not be perturbed by any of its components when they are either in a high impedance state or a power-off state. The generators and receivers must tolerate without damage the transmitted signals with their maximum amplitude within the specified limits.

Generators on the same multipoint line must have the same nominal d.c. offset voltage in order to operate correctly. However, generators with different d.c. offsets could be used on the same line provided that these differences be compensated at the common reference point.

2. Configurations

Several topological arrangements are to be considered:

• Cluster of circuits at the end of a line;
• Multidrop line;
• Star configuration.

Figure 9/V.11 illustrates a cluster configuration. Each line should be correctly terminated at the receiving end in order to avoid reflections and leads from that point to the receivers kept as short as possible.

Figure 10/V.11 illustrates a multidrop line. The presence of several generators along the line imposes the need to terminate the line correctly at both ends to avoid reflections. The length of the tapping connections along the line must be short enough to avoid mismatching of the main line. A length corresponding to a propagation delay of 1% of the unit interval of the signals seems to be an acceptable limit for the length of the tapping connection.

This tolerable propagation delay and other configurations are to be studied further.

The guidelines on cable length given in Figure 8/V.11 of Annex 1, assuming the same environmental conditions, apply equally to multipoint arrangements. Above 1 or 2 Mbit/s, however, the environmental conditions may be more difficult to control.

VOLUME VIII.1 — Rec. V.11

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Page 110

3. High Impedance State

3.1 Static Measurements

When in the high impedance state and with test loads of 50 ohms connected between each generator output point and point C, the magnitude of the voltage VY, measured between points A and B shall not exceed 4 mV whatever the logical condition of the generator input data lead (Figure 11/V.11).

When the generator is in the high impedance state, with voltages ranging between -6 V and +6 V applied between each output point and point C, as indicated in Figure 12/V.11, the magnitude of the output leakage currents IZA and IZB shall not exceed 150 µA.

The same condition applies under power-off condition.

3.2 Dynamic Measurements

During transitions of the generator output between the low impedance state and the high impedance state, the differential signal measured across a 100 ohm test load connected between the generator points A and B shall be such that the change in amplitude goes from 10% to 90% of the steady state voltage in less than 10µs.

Figure 9/V.11 - Clustered multipoint configuration

VOLUME VIII.1 - Rec. V.11

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Page 111

Distributed Multipoint Configuration

CCITT-6527-2

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High Impedance State Static Measurement

	Value
Vb

# matched

CCITT-6528-1

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Generator Output Leakage Current Measurement

	Value
Iba0l	< 150 μA
Iba1l	< 150 μA

CCITT-6529-2

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VOLUME VIII = Rec. V.11

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Page 112

Appendix F

Content of Defined ND Numbers

ND-06.007.01

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F-2

| CONTENT OF | | ND-156 | | CRATE SLOTS| | 32K | | | | RAM | | | | | | | | ND-147, 190 | | | | ADD DUAL | | | | PORT | | YES | | ND-145 | | 6017 | | ADD SINGLE | | | | PORT | | | | | | | | ND-158 | | | | 128K/32 BIT | | | | BANK | | | | | | YES | | ND-146 | | 6017 | | DUAL | | | | BANKS | | | | | | | | ND-144 | | | | 256K | | | | BANK | | | | | | | | ND-143 | | | | 128K | | | | BANK | | | | | |----------- |------------------------|----------------| | | CONTROL | | | | CALIBRATION| ADDRESS | | PORT | | CARD | | | | | PACKAGING | | ADDRESS | | | STORAGE: | | | DATA | | 0-32K | A | B | C | | | D | A | B | | 32-64K | PORT | PORT| PORT | | 64-96K | | | | | | | | | | | PORT | | | | | A | B | C | | 96-128K | D | A | B | | | | | | | 128-194K | PORT | | | | | | | | | 194-256K | A | B | C | | | D | A | B | | | | | | | | PORT | | | | | A | B | C | | | D | A | B | | | | | | | 6017 | 1144 | 1142 | | | | 1143 | 1143 | 1143 | | | 1145 | 1145 | | | | | | | | 6017 | 1144 | 1142 | 1142 | | | 1143 | 1143 | | | | 1145 | 1145 | | | | | | | | 6017 | | 1157 | | | | 1143 | 1143 | | | | 1142 | | 1144 | | | | | | | X-Y | | Y | C | | ADDRESS | B | A | C | | | PORT | C | B | | | | | | | 1 | 2 | 3 | 4 | | 5 | 6 | 7 | 8 | | 9 | 10 | 11 | 12 | | | | | | | DATA | | LOC | | | | | | | | ADDRESS | | | | | | | | | | CONTROL | 13 | 14 | 15 | | DATA | 16 | 17 | 18 | | | | | | | | | | | | 19 | 20 | 21 | 22 | | | 23 | 24 | 25 | | 26 | 27 | 28 | 29 | | STORAGE | 30 | 31 | 32 | | 0-32K | 32-96K | | |

BANK X | ND-06.007.01 | BANK Y

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Answer from Norsk Data

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