Page 1¶

DOMINO¶

Standard Hardware Description¶

ND-14.001.1 EN¶

Page 2¶

ACC EH¶

The ACC EH (Automatic Conversation Control Environment Handler) offers a seamless way to manage communication sessions. It efficiently handles sessions to optimize resource usage.

ALGC

Type	Init Sequence	Mode
DM	AUTO	ACTIVE
INT	MANUAL	PASSIVE
RST	INITIALIZED	STANDBY

Initialization Procedures

AUTO Mode
- Automatic start
- Monitors and adjusts session parameters
MANUAL Mode
- Requires user input
- Ideal for controlled environments

Operational Modes

ACTIVE: System actively manages and adjusts the communication session.
PASSIVE: System operates in the background, monitoring without intervention.
STANDBY: System is ready to activate when required, preserving power.

Conclusion

The ACC EH provides a robust framework for managing communication sessions. By automating key processes and providing flexible control options, it adapts to varying user needs effectively.

Page 3¶

DOMINO¶

Standard Hardware Description¶

ND-14.001.1 EN

Page 4¶

Table of Contents¶

System Overview
Hardware Configuration
Software Features
Networking and Connectivity
Security Measures
Support and Maintenance

System Overview¶

The system is designed to provide a comprehensive solution for modern businesses.

Hardware Configuration¶

Component	Specification
CPU	Quad-core 3.4 GHz
RAM	16 GB DDR4
Storage	512 GB SSD
Graphics	Integrated
Network Adapter	Gigabit Ethernet

Software Features¶

This system runs on a reliable operating system with the following features:

User-friendly interface
Advanced security options
Seamless integration with cloud services

Networking and Connectivity¶

The system supports various networking protocols to ensure smooth connectivity.

Security Measures¶

Robust security measures are implemented to protect data and ensure privacy.

Support and Maintenance¶

Comprehensive support and maintenance services are available to ensure system longevity.

Page 5¶

Preface¶


The product	The DOMINO standard hardware is the fixed hardware design implemented on all DOMINO controllers (DIOCs).
The Reader	This manual is intended for all personnel who require information about the standard hardware design of a DOMINO controller.
	The reader is assumed to have a general knowledge of digital hardware design.
The manual	This manual outlines the main features and design of the standard hardware used in a DOMINO controller. It is divided into four sections with two appendices containing the glossary and test connector pin-outs. The sections are:
	- 1. Introduction - a general overview of the DOMINO architecture.
	- 2. The DOMINO controller (DIOC) - a description of the function and design of the standard logic implemented in a DIOC.
	- 3. The MFbus Adapter (MFA) - a description of the main features of the DIOC interface to the MFbus via its on-board MFA.
	- 4. The OCTObus Adapter (OBA) - a description of the OCTObus control bus.
	These sections can be read individually.
Related manuals	The following manuals may be useful:
	The DOMINO Installation Guide (ND 14.003) - available June 1987
	The DOMINO Debug Guide (ND 14.004) - available June 1987
	The DOMINO Hardware Environment (ND 14.005) - available June 1987

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Table of contents¶

1 INTRODUCTION¶

Section	Title	Page
1.1	DOMINO I/O architecture	4
1.2	DOMINO hardware - the DIOC	6
1.3	The DIOC operating system - DOMINOS	8
1.4	DOMINO development system specification	9

2 THE DOMINO CONTROLLER (DIOC)¶

Section	Title	Page
2.1	DIOC Processing	15
2.1.1	The MC68020 Microprocessor	16
2.1.2	Master Control and Status Registers	16
	Master Control Register (MCR)	16
	Master Status Register (MSR)	18
2.1.3	Local DRAM	19
2.1.4	Local EEROM	21
2.1.5	Local EPROM	22
	EPROM memory switching	22
2.1.6	Address decoding	24
	DOMINO controller I/O space decoding	25
	Hardware implementation of the address decoding	27
2.1.7	Memory and I/O space protection system	28
	Control of the protection system	28
	The protect table	28
	Changing the protect table entries	30
	Protect table initialization	31
	Hardware implementation of the protect system	32
	OCTOubs reset protection and counter	34
2.1.8	Multifunction Peripheral (MFP) chip	37
	Programming the MFP	39
2.1.8.1	General Purpose I/O registers	41
	General Purpose I/O register (GPIP)	41
	Active Edge Register (AER)	41
	Data Direction Register (DDR)	42
2.1.8.2	The Interrupt Control registers	43
	Interrupt Enable Registers (IERA and IERB)	43
	Interrupt Pending Registers (IPRA and IPRB)	44
	Interrupt In Service Registers (ISRA and ISRB)	45
	Interrupt Mask Registers (IMRA and IMRB)	46
	Vector Register (VR)	46
2.1.8.3	MFP chip timers	47

Page 8¶

Timer Data Registers (TADR - TDDR)¶

Timer Control Registers (TACR and TBCR) ... 49
Timer Control Register (TCCR) ... 51

2.1.8.4 USART Operation¶

Sync Character Register (SCR) ... 52
USART Control Register (UCR) ... 53
Receiver Status Register (RSR) ... 55
Transmitter Status Register (TSR) ... 57

2.1.9 DIOC Interrupt System¶

Interrupt level 7 ... 60
Interrupt level 6 ... 61
Interrupt level 5 ... 62
Interrupt level 4 ... 62
Interrupt level 3 ... 62
Interrupt level 2 ... 63
Interrupt level 1 ... 64

2.1.10 Bus Error Operation¶

... 65

2.2 External DIOC Control¶

HALT and RESET operations ... 67
Cold start detection ... 69

2.3 DIOC Selftest¶

Test interface ... 72
User accessible tests ... 72
Error handling ... 72

2.4 DIOC Status¶

... 73

2.5 DIOC Card Design¶

... 74

3 The MFbus Adapter (MFA)¶

3.1 A Functional Overview of the MFbus Adapter (MFA)¶

Control block ... 80
Driver block ... 80
Ident block ... 80

3.2 MFA Interface to DOMINO Logic¶

Interface signal description ... 82

3.3 Signal Timing¶

Timing for MFbus access ... 85
Timing for string MFbus access ... 86
Timeout ... 87
Power failure ... 88

3.4 MFA Initialization and Requests¶

MFA initialization ... 89

3.5 Programming the MFA by the MFbus Controller¶

Read Module Type (RMT) ... 91
Read Master Status (RMS) ... 92

Page 9¶

Read ECO Level (RECOL) 93¶

Read Device Status (RDS) 93¶

Write Module Type (WMT) 93¶

Write Master Control (WMC) 94¶

Write OCTObus Initialization Values (WOI) 95¶

Write Device Control (WDC) 95¶

Write Limits (WLIM) 96¶

3.6 Programming the MFA by the DOMINO processor 98¶

Component	Page
The Timeout Counter	98
String Counter	99
Device Control Register	99
Slot Number	100
Read Status Register	100

4 THE OCTOBUS ADAPTER (OBA) 103¶

4.1 The OCTObus protocol 106¶

4.2 OCTObus nodes and the MASTER 108¶

4.3 The OCTObus allocation algorithm 108¶

4.4 OCTObus frame format 109¶

Frame format as seen from OCTObus output driver 111
Frame format as seen from OCTObus input driver 111
The Acknowledge field from the receiver 111

4.5 Hardware-generated OCTObus messages 112¶

4.6 Hardware-decoded messages 113¶

4.7 INT7 OCTObus Message Reset Register 114¶

4.8 OCTObus initialization and MASTER selection 115¶

4.8.1 Initializing an OCTObus node 116¶

Station number assignment 118
MFbus card crates 119

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Table of Appendices¶

Appendix	Title	Page
A	GLOSSARY	121
B	TEST CONNECTOR PIN-OUTS	125
	Index	129

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List of Figures¶

DOMINO I/O architecture .................................................... 4
Inside the general I/O controller ................................... 7
DOMINO-MONITOR and OPCOM interaction ....................... 8
The DOMINO I/O system ................................................ 13
Inside the DOMINO Controller ....................................... 14
The DOMINO Controller (DIOC) processor ..................... 15
Master Control Register (MCR) ...................................... 16
Master Status Register (MSR) ......................................... 18
Shadow memory switching ............................................. 23
The DOMINO address space decoding ............................ 24
Hardware implementation of address decoding .............. 27
Hardware implementation of the protection system ........ 32
Hardware implementation of the timeout function .......... 35
The watchdog timer ...................................................... 36
The Multifunction Peripheral chip block diagram ............ 37
The internal registers of the MFP ................................... 40
The MFP A and B timer operation .................................. 49
The interrupt system ................................................... 59
HALT and RESET selection .......................................... 68
Power failure detection ................................................ 69
Physical design of a DIOC ........................................... 74
A typical DOMINO design environment ......................... 78
Functional block diagram of the MFbus Adapter .............. 79
The MFA - DIOC logic interface ..................................... 81
MF’bus timing (read,write,address and data) ................... 85
MF’bus timing (string cycle) .......................................... 86
Write limit RAM format ............................................... 96
Implementation of the limit RAM .................................. 97
OCTObus implementation ............................................ 106
OCTObus transmission frame ..................................... 109
The OCTObus acknowledge bits ................................... 111
The acknowledge bits and retries .................................. 112
The OCTObus power-down message format .................. 113
The OCTObus power-up message format ....................... 113
The OCTObus hardware-decoded messages .................... 114
MFB system configuration ........................................... 115
A 1-bank (26 slots) card crate ...................................... 119
A 2-bank (2 by 13 slot) card crate ................................ 120

Page 14¶

Page Number¶

xii

Page 15¶

List of Tables¶

No.	Table Description	Page
1.	Decoding the protection bits	30
2.	Standard interrupt level assignment for DOMINO I/O	59
3.	Standard Interrupts for MFP chip	64
4.	Standard registers for MFbus communication	90
5.	MFA internal register addresses	98
6.	OCTObus data rate	107

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Chapter 1 Introduction¶

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Chapter 1 Introduction¶

DOMINO is the name of the hardware and software I/O (input/output) architecture designed for the ND-500/ND-5000. It is an architecture based on multiple-dedicated intelligent I/O controllers called DOMINO controllers (DIOCs).

This guide describes the hardware (and some software) features that are standard to all DIOCs. It includes the descriptions and circuit diagrams of these standard parts for those wishing to know more about DIOC design or wanting to design new I/O controllers in the DOMINO range.

Terminology

A subscript is used for:

register bits, e.g. MCR₈ is bit 8 of the MCR register
a signal's active state, e.g. DONE₀ is active low and DARY₁ is active high
octal numbers - denoted by ₈

Also:

set is used when the bit is a logical one
clear is used when the bit is a logical zero

Page 20¶

1.1 DOMINO I/O architecture¶

The figure below is a simplified view of an application using the DOMINO I/O system. It is a 32-bit environment based on the MFbus and the OCTObus.

Figure 1: DOMINO I/O architecture

Diagram Description

Component	Description
ND-500 CPU (ND-5000)	Local OCTObus
ND-110 CPU	Memory I/O Ports
MFB System Memory
MFbus Controller	MFbus (32 bit)
SMD-E Controller	To eight disk drives (max.)
Ethernet Interface	Interface link
Terminal Interface	User terminal

Figure 1. DOMINO I/O architecture

DIOCs have the hardware environment of the Multifunction Bus (MFB) system. The MFB is designed to support multiprocessing, a requirement of the DOMINO architecture.

Page 21¶

Chapter 1 Introduction¶

The main data carrier between system components, i.e. ND100(s), ND-5000(s), DIOCs and system memory is the Multifunction bus - MFbus. The MFbus is a full 32-bit bus in both the address and data paths. Semaphore cycles ensure safe access to data structures which are common to two or more processors.

The OCTObus is a serial bus optimized for fast handling of short messages. It is used for interprocessor synchronization and for passing configuration parameters during initialization. It can also be used as the communication medium between system components in an advanced development and maintenance system.

Page 22¶

Chapter 1 Introduction¶

1.2 DOMINO hardware - the DIOC¶

The DIOC central processing part, MFbus Adapter (MFA) and OCTObus Adapter are a standard design implemented by all DOMINO DIOC designs and form the hardware environment for device interface designs. This allows the shortest possible design cycles, as well as providing easy transport of software modules common to each controller.

The device interface may be designed to handle a few dedicated devices for high performance I/O or a selected mixture of devices to achieve a more compact solution for medium-range systems.

Increased functionality in the device handling can be built into specialized hardware and/or based on the available processing power of the DIOC processor.

The general DIOC contains a microprocessor, local memory, host interface (i.e MFB system interface) and a device interface.

Page 23¶

Chapter 1 Introduction¶

OCTObus¶

* OCTObus interface	* MFbus adapter
(OBCON)

* DOMINO controller processor		**
- MC68020
- Local RAM/EPROM/EEROM
- Interrupt system/RTC	FIFO/
	RAM

	Direct data
	path

* Console & Trace connector	Device-dependent circuitry
	**

: Standardized hardware for DIOCs
** : Device-dependent hardware

RTC : Real Time Clock.

Figure 2. Inside the general I/O controller

Page 24¶

1.3 The DIOC operating system - DOMINOS¶

The general processes to be run in the DIOCs will be under the control of the DIOC Operating System - DOMINOS.

DOMINOS is an enhanced version of PIOCOS (used by the PIOC family of I/O controllers). DOMINOS has a new and faster version of the PIOCOS process scheduler to minimize the context switching time between tasks. DOMINOS also includes an optimized version of XMSG.

To control the DIOCs a DOMINO-MONITOR is available. This communicates with the DIOC via the DOMINOS OPCOM module. Together, they handle the general control of the DIOCs and provide an extensive development and maintenance system.

host	target DIOC
DOMINO-MONITOR
	OPCOM

Figure 3. DOMINO-MONITOR and OPCOM interaction

Nucleus¶

The Nucleus system, used for communication, allows data to be moved between an unprivileged ND-500 user program and the DIOC I/O buffers by using ND-500 microcode. Hence, user processes can move data to/from the I/O handlers with no operating system overhead as no system calls are required.

From the ND-500, the data is represented as holes, with a hole number giving access to a data stream. From the DIOC, a hole is seen as a chain of buffers in a linear queue. For optimized speed, the hole operations are microcoded in the ND-500.

Page 25¶

1.4 DOMINO development system specification¶

The DIOC hardware is designed to support tools for prototype and production debugging, maintenance and software development. All DIOCs have a console connector as standard that can be used as an alternative access path to the DIOC if the normal communication path is not functioning.

The internal DIOC processor bus is available on connectors mounted in the front of the module. These connectors are designed to allow easy access to a logic analyser or the trace module for software debugging. The trace module (tracer) is controlled by explicit commands to the DOMINO-MONITOR or via implicit commands from the symbolic debugger.

Page 26¶

Chapter 1 Introduction¶

Page 27¶

11

Chapter 2 The Domino Controller (DIOC)¶

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Page 29¶

Chapter 2 The DOMINO Controller (DIOC)¶

The DOMINO Controller (DIOC) is an I/O handler for interprocessor communication within the MFB system environment. The typical configuration of a system is outlined below.

MFB System Memory

MFBbus
-----------------------
OCTObus
-----------------------
MFB
Controller


...

ND-5000 is directly attached to the MFB system

Figure 4. The DOMINO I/O system

Page 30¶

Chapter 2 The DOMINO Controller (DIOC)¶

The DOMINO system allows dedicated I/O controllers to be accessed directly by the ND-500 and ND-100 processors, as well as by other I/O controllers.

All DOMINO Controllers (DIOCs) have a standard hardware architecture. Controller-dependent (device-dependent) hardware is added to the standard design to implement a DIOC's particular function (SMD controller, Ethernet, etc.).

A DIOC has the following hardware architecture:

OCTObus interface (OBCON)	* MFbus adapter
* DOMINO controller processor	**
- MC68020	FIFO/Direct
- Local RAM/EPROM/EEROM	RAM data
- Interrupt system/RTC	path
* Console & Trace connector	Device-dependent circuitry **

: Standardized hardware for DIOCs
** : Device-dependent hardware

RTC : Real Time Clock.

Figure 5. Inside the DOMINO Controller

The basic building blocks are:

microprocessor (MC68020)
local memory

Page 31¶

Chapter 2 The DOMINO Controller (DIOC)¶

host (MFB system) interface
device interface

2.1 DIOC Processing¶

The central processing part of the DIOC is illustrated below.

+----------------------------+
| control and status         |
| registers                  |
+----------------------------+
        |       |       |       |       |         |       
+-------+-------+-------+-------+-------+---------+-------+
|       |       |       |       |       |         |       |
+---+   +---+   +---+   +---+   +---+   +---+     +---+   |
|   |   |   |   |   |   |   |   |   |   |   |     |   |   |
|   |   |   |   |   |   |   |   |   |   |   |     |   |   |
| D |   | E |   | E |   | A |   | P |   | M |     | P |   |
| R |   | P |   | E |   | d |   | r |   | P |     | r |   |
| A |   | R |   | R |   | d |   | o |   | F |     | o |   |
| M |   | O |   | O |   | r |   | t |   | P |-----| t |   |
|   |   | M |   | M |   | e |   | e |   +---+     | e |   |
|   |   |   |   |   |   | s |   | c |             | c |   |
|   |   |   |   |   |   | s |   | t |             | t |   |    
+---+   +---+   +---+   +---+   +---+             +---+   |
        +-----------+                             |
        | interrupt |                             |
        | system    |                             |
        +-----------+                             |
        | panel     |                             |
        | functions |                             |
        +-----------+                             |
                                                  |
+--------------+                                  
| MC68020      |                                  
|              |
| 1            |
| 2            |
+--------------+

MC68020 : MC68020 microprocessor  
1 : MC68020 Address bus  
2 : MC68020 Data bus  

*Figure 6. The DOMINO Controller (DIOC) processor*

Page 32¶

2.1.1 The MC68020 Microprocessor¶

The MC68020 is a 32-bit microprocessor dedicated to the I/O processing required by the DIOC card.

Detailed and introductory descriptions of the MC68020 can be found in vendor manuals. However, details of the processor relevant to the DIOC design are given in this manual.

2.1.2 Master Control and Status Registers¶

Two registers monitor and affect DIOC activity:

Master Control Register (MCR)
Master Status Register (MSR)

They are located within the I/O address space of the controller.

Master Control Register (MCR)¶

Address: FF8100 hex
Read/write

		L	R	E	O	B	S	M	P	S	M	I	R
L	L	L	R	E	O	B	C	D	R	E	P	N	A
E	E	B	C	O	D	R	E	F	R	E	P	N	A
D	D	E	O	C	I	K	T	P	O	T	E	V	M
1	2	R	L	R	S	M	B	R	T	P	R	P	M
*	*

Figure 7. Master Control Register (MCR)

The register bits control the following DIOC functions:

Page 33¶

Chapter 2 The DOMINO Controller (DIOC)¶

mnemonic	meaning	bit=1	bit=0
RAMM	RAM Mode	normal	EPROM
INVP	Inverse Parity	yes	no
MPER	Parity Checking	yes	no
SETP	Set Priority Bit	yes	no
PROT	Protect System On	yes	no
MFPR	Enable MF'bus protection system	yes	no
SETB	Set Breakpoints	yes	no
BRKM	Break Mode	yes	no
ODIS	Disable OCTObus tcvr interrupt	yes	no
EOCR	Enable OCTObus reset message	no	yes
RCOL	Reset Cold Start Bit	yes	no
LBER	Long bus error (~ 500μs)	yes	no †
LED2	Reset/Hardware fault	no/okay	yes
LED1	Talking to other DIOCs	yes	no

tcvr : transceiver

† If the bit is zero the local timeout for the bus error is approximately 2μs.

If the MCR is cleared (all zeros) the DIOC switches to EPROM (shadow memory) execution. The following events cause MCR to be cleared:

power failure
reset
fatal DIOC hardware error, e.g. parity error

Page 34¶

Master Status Register (MSR)¶

Address: FF8106 hex
Read only

15	0
* * * * *	C P R O R
	O R O P R
	L O 0 * *
	D T * T T
	S S * S S
	1 2 * 1 2

*not used

Figure 8. Master Status Register (MSR)

This register can be read only. Set bits indicate:

mnemonic	meaning	bit=1	bit=0
TPRES	trace module present	no	yes
ROR	data in OCTObus field	yes	no
COLD	cold start active	yes	no

PROTU1 and PROTU2 : user protect-table entries
PROTS1 and PROTS2 : supervisor protect-table entries
(See Section 2.1.7 on the Memory and I/O space protection system.)

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Chapter 2 The DOMINO Controller (DIOC)¶

2.1.3 Local DRAM¶

A DIOC can have a maximum of 8 Mbytes of local DRAM (Dynamic RAM).

The DRAM can be accessed by the MC68020 and onboard DMA devices but NOT via the MFbus adapter. It holds the application programs and local data structures, allowing the DIOC to execute programs without MFbus contention. Application programs are copied from the MFB system memory to DRAM by the processor during system bootstrap. (The bootstrap program is held in EPROM.)

protection

Processor and local DMA accesses are checked for legality before a memory cycle is performed. An attempt at accessing protected memory results in a Bus Error (BERR) and the cycle is aborted. A BERR is not notified in the case of an illegal DMA access. (see Section 2.1.9.)

parity

Each 32-bit word in DRAM is stored with a 4-bit parity code to detect memory errors. The parity circuitry can be tested by forcing a parity error into the DRAM. This is done by setting the INVP (inverse parity) bit in the Master Control Register (MCR) so that writing to DRAM will cause a parity error. INVP should be reset to avoid the exception (interrupt) stack from being written with parity errors and a level 7 interrupt (LMPERR) requested.

parity errors

A parity error will cause: - an immediate switch to EPROM - a level 7 interrupt (BPFAIL) to the processor - an OCTObus message As a result the DIOC will execute a recovery routine.

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Chapter 2 The DOMINO Controller (DIOC)¶

breakpoints¶

The DRAM can also be used as a breakpoint RAM. Parity is not checked in this mode. To select the breakpoint RAM:

select disable parity mode - set MCR₂
check inverse parity is not selected - clear MCR₁
disable break mode - clear MCR₇
enable set breakpoint mode - set MCR₆
clear the entire breakpoint RAM by writing '1's to all addresses in main memory
set a breakpoint by writing a zero to the required breakpoint address
disable set breakpoint mode - clear MCR₆
enable break mode - set MCR₇

All accesses to the address where the breakpoint is set will generate a bus error. To check a bus error is generated by a breakpoint and not by anything else, you should check that the DIOC is running in break mode by reading the MCR; the INTSOURCE register will give the source of a bus error not caused by a breakpoint (see Section 2.1.9).

To clear the breakpoints:

exit break mode - clear MCR₇
enable set breakpoint mode - set MCR₆
write '1's to the addresses of the breakpoints
disable set breakpoint mode - clear MCR₆

You must reinitialize the parity system to enable it:

Page 37¶

Chapter 2 The DOMINO Controller (DIOC)¶

disable break mode - clear MCR₇

disable set breakpoint mode - clear MCR₆

read and write back the entire memory

re-enable parity system - set MCR₂

2.1.4 Local EEROM¶

The local EEROM can be used to store and retain run-time information such as user statistics, DIOC parameters.

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Chapter 2 The DOMINO Controller (DIOC)¶

2.1.5 Local EPROM¶

A maximum of 4 Mbytes of EPROM can be addressed by a DIOC. The EPROM typically contains the routines: OCTObus driver, OPCOM handler, copy routines, self-tests, etc..

The EPROM is accessed after:

controller reset
power failure
fatal hardware error (MPERR - DRAM parity error)

The EPROM contains the software to establish an 'off-line' communication channel which, via the OCTObus, generates commands to bootstrap from MFbus memory or recover from a power failure. The local RAM undergoes a 'shadow memory switch' during the process.

EPROM memory switching¶

The Master Control Register (MCR) controls the memory switching procedure via MCR', the RAM-M bit. A reset or serious error (such as bootstrap or power failure) clears this bit, switching memory access to EPROM.

The MC68020 will access EPROM from within an address range of 0 to 3FFFFF hex. The RAM area that has the equivalent address range to the EPROM (0 to 3FFFFF hex) is said to be 'under the shadow' of the EPROM and can be accessed by addressing 800000 to BFFFFF hex.

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Chapter 2 The DOMINO Controller (DIOC)¶

MC68020 address¶

RAM-M = 0¶


Shadow RAM	BFFFFF
	800000
EPROM	3FFFFF
	000000

Figure 9. Shadow memory switching

Once the processor has recovered from a reset or parity error the EPROM program switches its memory address range to 800000 to BFFFFF hex, allowing the 'shadow' RAM to be addressed between 0 and 3FFFFF hex.

MC68020 address¶

RAM-M = 1¶


EPROM	BFFFFF
	800000
RAM	3FFFFF
	000000

Page 40¶

Chapter 2 The DOMINO Controller (DIOC)¶

2.1.6 Address decoding¶

The MC68020 within a DIOC can access a maximum of 2 Gbytes of MFbus memory, 8 Mbytes of local DRAM and 4 Mbytes of local EPROM.

The memory area, as seen by the MC68020, is addressed as follows:

Address bit 31 = 0	Address bit 31 = 1
1FFFFFF	7FFFFFFF
16 Mbytes for alternate bus use	2GB max.
FFFFFF	. .
E00000	. .
C00000	. .
800000
4MB max.
3FFFFF


EPROM SHADOW
Local Memory	MFB System Memory
(EPROM)	(RAM)
(DRAM)

Figure 10. The DOMINO address space decoding

Address bit 31 determines whether the memory access is to MFbus system (global) or local memory. The processor address selects the address range as follows:

Page 41¶

Chapter 2 The DOMINO Controller (DIOC)¶

bit 31	address range
0	local
1	global

However, the MFbus will always see bit 31 as a logical zero.

DOMINO controller I/O space decoding¶

Addresses not leading to an EPROM or RAM cycle are defined as I/O space addresses.

The I/O space of a DIOC is mapped onto a 64 Kbyte area from address D00000 to FFFFFF hex. This area is divided as follows:

Address	Description
FFFFFF	EEPROM
FFC000	System I/O
FF8000	Reserved
FF4000	Device I/O
FF0000	Device I/O
E00000	Tracer
C00000

System I/O¶

The system I/O is address space given to registers/devices standard to all DOMINO controllers. It is allocated to:

Page 42¶

Chapter 2 The DOMINO Controller (DIOC)¶

I/O Address	Device
FF8000-FF803F	MFP interrupt/terminal
FF8040-FF807F	BADAP MFbus control
FF8080-FF80BF	OBCON
FF80C0-FF80FF	OCTObus input FIFO
FF8100-FF817F	DIOC general registers
FFBFC0-FFBFFF	Bus error for selftest †

† This region is used during selftest to check the bus error detection circuitry. (See section 2.3 on DIOC selftest.)

The MFP (Multifunction Peripheral chip) addresses are described in detail in Section 2.1.8.

The DIOC general registers are:

Address	Description	mnemonic
FF8100	Read/Write Master Control Register	MCR
FF8102	Read interrupt source for level 7/ Clear interrupt source for level 7	INTSOURCE
FF8104	XCLK-trig pulse to test connector
FF8106	Read Master Status Register	MSR
FF8108	Read 32-bit counter (bits 0-31)
FF810C	Reset watchdog
FF810E	Reset INT7 OCTObus message
FF8110	)
.	)
.	Not used
.	)
FF817F	)

Note: All registers are 16-bit EXCEPT the 32-bit counter.

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device I/O¶

The device I/O is the address space given to device-dependent registers/devices, their specific use depends on the DIOC selected. There are two areas of device I/O space, the lower block (E00000 to FF0000) is selected by IOSEL2 and the upper block selected by IOSEL1.

tracer¶

The address area from C00000 to E00000 (2 Mbytes) has been reserved for a DOMINO controller trace module. The trace module defines its own use of the available address space.

Hardware implementation of the address decoding¶

Main decoding	I/O decoding
	CS901
PROMSEL	CSBADA₀ₚ
RAMSEL	CSOCTO₀
MFB	ROCTO₀
IOSEL1	REGSEL
IOSEL2	DEVSEL₀
SETP	SETPROT₀
RAM-M	EEPROM₀
CPUSPACE	RWD₀
	TRAP₀

Figure 11. Hardware implementation of address decoding

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2.1.7 Memory and I/O space protection system¶

DOMINO controllers have an extensive protection system to prevent unauthorized access to local system memory and I/O address space. Global memory access is protected within the MFbus adapter (MFA).

The memory access cycle will be aborted if an unauthorized access of a protected address is attempted and a Bus Error (BERR) generated (see Section 2.1.9).

A DMA cycle against a protected address will be handled in the same way. DMA cycles have the same protection as user data cycles.

Control of the protection system¶

The protection system is turned ON by setting the PROT bit in the Master Control Register - MCR₄. After a reset or a power failure this bit is zero, i.e. the protection system is OFF.

The protect mode(s) required MUST be set in the protect table before PROT is set.

The protect table¶

The protect table is a 4 by 16 K bit static RAM with each 4-bit entry in the protect table representing a Kbyte of the 16 Mbyte on-board address space.

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The 4-bit field defines the protection level of the Kbyte segment:

bit	name	mode
4	S1	supervisor
3	S2	supervisor
2	U1	user
1	U2	user

A DIOC has two modes of operation:

Supervisor
User

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The protection bits are decoded as follows:

S1	S2	U1	U2	S	U	Used
0	0	0	0	F	F	Common clean code
0	0	0	1	F	R	*
0	0	1	0	F	RF	PIOC ON: Any access except User Write
0	0	1	1	F	RW	PIOC OFF: Any access
0	1	0	0	R	F	User clean code
0	1	0	1	R	R	Total protected data
0	1	1	0	R	RF	User dirty code
0	1	1	1	R	RW	User private data
1	0	0	0	RF	F	*
1	0	0	1	RF	R	*
1	0	1	0	RF	RF	Common dirty code
1	0	1	1	RF	RW	*
1	1	0	0	RW	F	*
1	1	0	1	RW	R	System public data
1	1	1	0	RW	RF	*
1	1	1	1	RW	RW	User public data

this combination of supervisor and user protection bits should not be used

F fetch
R read
W write
S supervisor
U user

Table 1. Decoding the protection bits

Changing the protect table entries¶

A protect table entry can be set or cleared by SETP (MCR₃). This ensures that any memory write access is a protect table write operation and will not affect memory.

The 4-bit protect table entry for the segment can then be written to with the protection required.

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Protect table initialization¶

The routine executed to initialize the protect table should not be interruptable, as during an interrupt, the processor stack is written to the protect table will be lost.

A fatal power failure (standby power lost) will cause a cold start. This means that all protect table entries have to be reinitialized. (see Section 2.2.)

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Hardware implementation of the protect system¶

    MCD9 ─────
    MCD8 ─────
    MCD1 ─────
    MCD0 ─────
              |
           D 1234
    A 23 ────────
    22 ──────────
    21 ──────────
    20 ──────────
    19 ──────────
    18 ──────────
    17 ──────────
    16 ──────────
    15 ──────────
    14 ──────────
    13 ──────────
    MCR──────────
    12 ──────────
    11 ──────────
    10 ──────────
    9 ───────────
               WR
               CS1
    8 ──────┌──CS2
               OE
    Y 1234───┘
      __
    IDT71981-45

    SETPROT──────────
    WRITE────────────
    S4/5─────────────
    MCR──────────────
    A10──────────────

PAL22V10
AS0	PROTU1	23
1	PROTU2	22 ── To MSR
U2	PROTS1	21 ── INTSOURCE0
U1	PROTS2	20
S2	CPUTRAP	19 ── BERR
S1	DMATRAP0	18 ── I3 on 68901
CFCO	SEL16	17
CFC1	MFPRO	16
CFC2	BGACK	15
MFCYC	DEVREQ0	14
PROT-M0	RW0	13
T3		11

Figure 12. Hardware implementation of the protection system

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PROT-M and SETPROT are bits PROT and SETP in the Master Control Register (MCR).

CFCO-CFC2, WRITE and AS are outputs from processor.

T3, a timing signal, becomes active on the falling edge of the second period in the bus cycle. MFCYC0 is active when there is a cycle against the MFbus and not a local cycle.

CPUTRAPO generates a BERR to the processor.

DMATRAPO is an interrupt source for the 68901 (MFP) interrupt controller.

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OCTObus reset protection and counter¶

There are two ways by which the OCTObus can reset a controller.

software message
timeout from a watchdog timer

message¶

The OCTObus software message gives the following reset information:

a reset message will be sent
the controller must enable OCTObus reset.

The controller is then ready to receive and accept the reset message from the OCTObus.

timeout¶

Timeout from a watchdog timer:

the controller defines itself as dead by a timeout from its watchdog timer
the timeout enables the OCTObus reset signal

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PAL2ORA10¶


OBMCD00	I00	RESET1	B0
OBMCD01	I1	IHALT	B1	RCOUNT
OBMCD02	I2	OCINT7	B2	RFO
OBMCD03	I3	RESCOUNT	B3
OBMCD04	I4		B4	OCPALRESET
OBMCD05	I5		B5	RESOCINT
OBMCD06	I6		B6	ENOCRES
OBMCD07	I7		B7
OBMCD14	I8		B8
OBMCD15	I9	SIR	B9
	OE	RCOUNT	OE
		16 bits

LS292


H
A	TOUT
B	Q
C
D
E
WDOGRES	CLR TP1
16CLK	CLK1 TP2
	CLK2 TP3

Figure 13. Hardware implementation of the timeout function

The output signals RESET1, IHALT, OCINT7 and RESCOUNT are hardware decoded OCTObus messages. The PAL decodes the message on the OBMC data bus along with the input signals (denoted by arrows in the diagram) to generate the control output signals.

WDOGRES resets the counter (watchdog timer) and deactivates the TOUT (timeout) signal. If the address decoded as WDOGRES does not occur at regular intervals (as set by the value of the inputs A-E), TOUT becomes active and will enable the OCTObus reset signal.

The input values for A-E in Figure 13 will give

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a timeout of approximately 1 second.

Writing a one to the address decoded as ENOCRES enables the OCTObus reset signal; writing a zero to the same location will disable a reset from OCTObus. This input can also be read back.

The watchdog timer is implemented as follows:

Watchdog Timer Diagram

Figure 14. The watchdog timer

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2.1.8 Multifunction Peripheral (MFP) chip¶

The 68901 Multifunction Peripheral chip (MFP) combines many of the peripheral functions in a DIOC design into one chip. Included are:

eight parallel I/O lines
interrupt controller for 16 sources
four timers
one full-duplex serial port for Asynchronous or Synchronous communication channel (USART)

A functional block diagram of the MFP is given below:

D        CPU
A0-7     interface
A0-4
power
and
control
         interrupt
IEI      control
IACK
IEO
INTR

         Timers

         C and D, TCO,TDO
         A and B   XTAL1,2
                   TAO,TBO

                        TAI,TBI
                          SO

                        USART

                        RC
                        TC
                        RR
                        TR

                        SI

general purpose
I/O interrupts
                        I0-7

Figure 15. The Multifunction Peripheral chip block diagram

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Internal Control Logic¶

This block contains the following interface signals:

Clock input for internal timing of the MFP (CLK)
+5V power source (Vcc) and a signal ground (Vss)
Active-low RESET signal

Asserting the RESET signal will:

Disable the USART receiver and transmitter
Stop all timers and force their outputs low
Disable all interrupt channels and clear all pending interrupts
Tri-state the General Purpose I/O Port (GPIP) lines
Clear all internal registers (except the timer, USART data and transmit status registers)

Timers¶

Each timer generates an output signal which changes state with each timer cycle. The period of the output signal is equal to two cycles (TAO, TBO, TCO and TDO). In addition, Timer A and B have one input each (TAI and TBI) for event and pulse width measurement. These inputs are connected to the interrupt channels I4 and I3.

USART¶

The USART has:

One serial input (SI) and one serial output (SO) line.
One receiver ready (RR) and one transmitter ready (TR) active-low line. RR and TR allow DMA operations and signal receive buffer full or transmit buffer empty status.

The USART has a receiver clock (RC) and a transmitter clock (TC).

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IO-I7 lines¶

These lines may be used as interrupt inputs and/or I/O lines. When used as interrupt lines, the active signal edge is programmable. A Data Direction Register (DDR) is used to define which lines are to be tri-state inputs or push-pull compatible outputs.

Interrupt Control¶

The active-low INTR output signal is used to request an interrupt. It is negated by an active-low interrupt acknowledge (IACK) signal from the CPU or by resetting the pending interrupt.

The active-low Input Enable Out (IEO) line signals to lower-priority peripherals that no higher-priority peripheral is requesting service.

The active-low Interrupt Enable In (IEI) signals the MFP that no higher-priority device is requesting service.

Programming the MFP¶

MFP control registers are accessed by the DIOC processor at the address:

MFP register = FF8000 + <MFP register no.> (hex)

The read and write instructions are performed by even-addressed registers, of the format:

15								7							0
x	x	x	x	x	x	x	x	D	D	D	D	D	D	D	D

The lower byte of the word is used when reading or writing to the MFP registers.

The MFP uses 24 registers for processor control of all its functions. The registers and their corresponding addresses are listed overleaf:

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Chapter 2 The DOMINO Controller (DIOC)¶

reg no.	mnemonic	description
0	GPIP	General-purpose I/O
2	AER	Active Edge Register
4	DDR	Data Direction Register
6	IERA	Interrupt Enable Register A
8	IERB	" " " B
A	IPRA	Interrupt Pending Register A
C	IPRB	" " " B
E	ISRA	Interrupt In-Service Register A
10	ISRB	" " " B
12	IMRA	Interrupt Mask Register A
14	IMRB	" " " B
16	VR	Vector Register
18	TACR	Timer A Control Register
1A	TBCR	" B "
1C	TCDCR	Timer C & D Control Register
1E	TADR	Timer A Data Register
20	TBDR	" B "
22	TCDR	" C "
24	TDDR	" D "
26	SCR	Sync Character Register
28	UCR	USART Control Register
2A	RSR	Receiver Status Register
2C	TSR	Transmitter Status Register
2E	UDR	USART Data Register

Figure 16. The internal registers of the MFP

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2.1.8.1 General Purpose I/O registers¶

The GPIP (General-purpose I/O Interrupt Port) has three registers, providing eight lines defined as either input or output under software control. They are:

The General Purpose I/O Data Register
The Active Edge Register
The Data Direction Register

In addition, each line can generate an interrupt on either the positive going edge or the negative going edge of the input signal.

A * in the following register descriptions denotes an unused bit.

General Purpose I/O register (GPIP)¶

Address: FF8000	7	6	5	4	3	2	1	0
GPIP	7	6	5	4	3	2	1	0

Active Edge Register (AER)¶

Address: FF8002	7	6	5	4	3	2	1	0
GPIP	7	6	5	4	3	2	1	0

The trigger condition for each input is given by the logic state of the appropriate bit:

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Chapter 2 The DOMINO Controller (DIOC)¶

State	Trigger on:
0	falling edge
1	rising edge

To avoid false interrupt operation, this register should be initialized before the interrupt is enabled. (See Interrupt Enable Registers A and B.)

Data Direction Register (DDR)¶

This register determines whether a line is input or output.

   7                     0
Address: FF8004
| GPIP 7 | GPIP 6 | GPIP 5 | GPIP 4 | GPIP 3 | GPIP 2 | GPIP 1 | GPIP 0 |

State	Function
0	Input
1	Output

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2.1.8.2 The Interrupt Control Registers¶

The Interrupt Control Registers provide control the interrupt processing of all MFP I/O facilities. They allow the programmer to enable or disable any of the 16 interrupts. They can:

mask interrupts
give access to pending interrupts status
give access to the in-service status of interrupts

Interrupt Enable Registers (IERA and IERB)¶

	GPIP	GPIP	TIMER	RX	RX	TX	TX	TIMER
IERA	7	6	A	Buff.	Error	Buff.	Error	B
Address:				Full		Empty
FF8006

	GPIP	GPIP	TIMER	TIMER	GPIP	GPIP	GPIP	GPIP
IERB	5	4	C	D	3	2	1	0
Address:
FF8108

Interrupts are enabled/disabled by setting/clearing the appropriate bit:

State	Function
0	Interrupt disabled
1	Interrupt enabled

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Interrupt Pending Registers (IPRA and IPRB)¶

	GPIP 7	GPIP 6	TIMER A	RX Buff. Full	RX Error	TX Buff. Empty	TX Error	TIMER B
IPRA Address: FF800A

	GPIP 5	GPIP 4	TIMER C	TIMER D	GPIP 3	GPIP 2	GPIP 1	GPIP 0
IPRB Address: FF800C

When an interrupt is received on an enabled channel, its corresponding bit in the Interrupt Pending Register will be set.

When the same interrupting channel is acknowledged, and the interrupt vector has been passed on, the bit in the Pending Register will be cleared.

Both read and write actions are allowed on these registers. Thus a pending interrupt can be cleared without going through the acknowledge sequence by writing a "0" to the Interrupt Enable Register.

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Interrupt In Service Registers (ISRA and ISRB)¶

ISRA Address: FF800E	7					RX
	GPIP 7	GPIP 6	TIMER A	RX Buff. Full	RX Error	TX Buff. Empty	TX Error	TIMER B

State	Function
0	Interrupt not in service
1	Interrupt in service

Bits are set in these registers on two occasions (see Vector Register specification):

software-end-of-interrupt mode
software reset

When an interrupt channel is serviced, no lower priority channels are allowed to interfere. Interrupts received on lower or equal levels will be latched into the Interrupt Pending Registers. These interrupts are not serviced until the corresponding bit in the In-Service register is cleared (by software). An interrupt is cleared by writing a "0" in the appropriate bit position. The registers can be read at any time.

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Interrupt Mask Registers (IMRA and IMRB)¶

7							0
IMRA Address: FF8012	GPIP 7	GPIP 6	TIMER A	RX Buff. Full	RX Error	TX Buff. Empty	TX Error


IMRB Address: FF8014	GPIP 5	GPIP 4	TIMER C	TIMER D	GPIP 3	GPIP 2	GPIP 1

These registers are used to block an interrupt request to a channel. Read and write operations are allowed.

State	Function
0	Interrupt channel blocked
1	Interrupt channel free

Vector Register (VR)¶

7						0
Address: FF8016	V7	V6	V5	V4	S	*

The upper four bits of this register identify the interrupt channel. Bit three, the S-bit, defines the End Of Interrupt Mode.

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State	Function
0	Automatic End
1	Software End

Automatic End
The interrupt is cleared when the acknowledge function is finished by passing the interrupt vector.

Software End
The In Service Interrupt is cleared by writing a "0" to the corresponding bit in the In Service Register.

2.1.8.3 MFP chip timers¶

The MFP has four timers. Timer A and B are full-function timers which can perform the following tasks:

basic delay functions
pulse width measurement
waveform generation

Timers C and D are delay timers only.

The timers are programmed via three Timer Control Registers and four Timer Data Registers.

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Timer Data Registers (TADR - TDDR)¶

7                                           0
---------------------------------------------
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---------------------------------------------

The addresses of the data registers for the timers are:

Timer	Address	Mnemonic
A	FF801E	TADR
B	FF8020	TBDR
C	FF8022	TCDR
D	FF8024	TBBR

A new word is not loaded into the timer until it counts through to '1' when the timer is running.

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Timer Control Registers (TACR and TBCR)¶

TACR¶

Address: FF8018

7	6	5	4	3	2	1	0
*	*	*	TIMER	AC3	AC2	AC1	AC0
			A
			Reset

TABR¶

Address: FF801A

7	6	5	4	3	2	1	0
*	*	*	TIMER	BC3	BC2	BC1	BC0
			B
			Reset

Bits 0-3 define the operation mode of the timer:¶

C3	C2	C1	C0	Timer mode	Function
0	0	0	0	Stop mode	Stop timer
0	0	0	1	Delay mode	Prescale by: 4
0	0	1	0		10
0	0	1	1		16
0	1	0	0		50
0	1	0	1		64
0	1	1	0		100
0	1	1	1		200
1	0	0	0	Event count mode
1	0	0	1	Pulse width mode	Prescale by: 4
1	0	1	0		10
1	0	1	1		16
1	1	0	0		50
1	1	0	1		64
1	1	1	0		100
1	1	1	1		200

Figure 17. The MFP A and B timer operation

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stop mode¶

The timer contents remain unchanged but the residual count in the prescaler is lost.

Delay mode¶

The prescaler is always active. A count pulse is given to the main timer each time a given number of timer clock cycles has elapsed.

The output from the timer is dependent upon the Timer Data register. If the prescaler is programmed to divide by 10 and the data register is loaded with 100, a timeout pulse will occur every 1000 cycles of the timer clock. The output clock period will be 2000 clock cycles.

Pulse Width Mode¶

In this mode, Timers A and B can measure pulses on I/O channels 4 and 3. The accuracy depends upon the Prescaler value.

The Active Edge Register (AER) specifies the triggering mode as follows:

State	Trigger on:	Counter:
0	falling edge	start
1	rising edge	stop

The counter generates a CPU interrupt when it stops. The contents of the Timer Data Register gives the pulse width (the number of counts).

The outputs of the timers can be forced low by:

device reset
setting the reset bit (TACR₄ or TBCR₄)
during Timer Write

In addition the output(s) will toggle on each Timer Out pulse.

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Timer Control Register (TCCR)¶

Address: FF801C

7				0
*	CC2	CC1	CC0	*
DC2	DC1	DCO

bits 4-6 Timer C mode.
bits 0-2 Timer D mode.

The modes are:

C2	C1	C0	Timer mode	Timer function
0	0	0	stop
0	0	1	delay	Prescale by 4
0	1	0		10
0	1	1		16
1	0	0		50
1	0	1		64
1	1	0		100
1	1	1		200

2.1.8.4 USART operation¶

The USART has the following registers:

1 Sync Character
1 Control
2 Status
1 Data

Variable word length and Start/Stop bits are selectable by software. Syncwords are

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continuously transmitted when no other data is available for transmission (Buffer Empty condition). The handshake control lines RR (Receiver Ready) and TR (Transmitter Ready) allow DMA operation.

Sync Character Register (SCR)¶

Address: FF8026	7							0
	D7	D6	D5	D4	D3	D2	D1	D0

Underrun condition

When underrun occurs in the Synchronous transmission mode, the character in the SCR will be transmitted until a new word is loaded into the transmit buffer.

Parity

If the sync character is less than 8 bits, the Parity bit has to be loaded into the SCR along with the sync character.
If the SCR character is 8 bits, the MFP will calculate the parity and assert the parity bit when transmitting the sync character.

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USART Control Register (UCR)¶

Address: FF8028

7						0
Div 16/1	WL1	WL0	ST1	ST0	Parity Even/Odd	*

bit 7¶

State	Frequency of data clock
0	1:1
1	1:16

bits 5 and 6¶

These two bits define the word length of the transmission.

WL1	WL0	Word length
0	0	8 bits word
0	1	7 bits word
1	0	6 bits word
1	1	5 bits word

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bits 3 and 4¶

These two bits select the data format.

bits:	Data	number of bits:
WL1 WLO	Format	Start
0 0	Sync	0
0 1	Async	1
1 0	Async	1
1 1	Async	1

bit 2:¶

State	Function
0	parity not set
1	parity

When parity is enabled, the transmitter will calculate and add the parity code to the word to be transmitted and the receiver will check it.

bit 1:¶

IF parity is enabled:

State	Function
0	Odd Parity
1	Even Parity

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Receiver Status Register (RSR)¶

The receiver generates two interrupts on:

buffer full
receiver error

Each time a new word is loaded into the receive buffer, a new set of flags is latched into the RSR register. Thus the RSR should be read before reading the USART Data Register.

7							0
Address: FF802A	BF	OE	PE	FE	F/S	M/CIP	SS

BF - bit 7: Buffer Full¶

BF is set when the buffer is full. It is cleared when the USART Data Register is read.

OE - bit 6: Overrun Error¶

This bit is set when the receive buffer is not read before a new word comes in. The word currently in the receive buffer is not overwritten and OE will not be set (and an interrupt generated) until the word currently in the buffer has been read. New data cannot be shifted into the buffer until OE has been cleared by reading the UCR.

PE - bit 5: Parity Error¶

This bit is set when the word is shifted from the shift register to the receive buffer if an error condition has occurred.

FE - bit 4: Frame Error¶

The bit is set in Asynchronous mode when a non-zero data word is received without its following stop bit. The bit is set and cleared when a word is transmitted into the receive buffer.

F/S - bit 3: Found/Search¶

This bit is used as follows:

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In synchronous mode:
The bit is set or cleared by writing it to the RSR register. When cleared, the receiver is in search mode and a bit-by-bit comparison of the incoming data to the character in the Sync Character Register is made. The word length counter is disabled. When a match is found F/S is set, the word length counter restarted and an interrupt generated on the receive-error channel.

In asynchronous mode:
F/S is set if an all-zero data word is received without a following stop bit. F/S will remain set until a non-zero bit is received or the RSR register is read. The Break flag, bit 3 of the Transmitter Status register (TSR) is not set if the data buffer is full.

M/CIP - bit 2: Match/Character In progress¶

This bit functions as follows:

In synchronous mode:
M/CIP is set each time the word transferred to the receive buffer matches the sync character. It will be reset each time the word does not match.

In asynchronous mode:
M/CIP represents the character in progress. It will be set by the start bit and cleared at the end of the word.

SS - bit 1: Sync Strip Enable¶

If set, incoming words that match the Sync Character are not loaded into the receive buffer and the buffer-full flag (bit 7 - BF) will not be set.

RE - bit 0: Receive Enable¶

Clearing this bit will disable the receiver immediately and clear all the bits in the RSR register. Setting the bit enables the receiver.

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Transmitter Status Register (TSR)¶

Address: FF802C

7						0
BE	UE	AT	END	BREAK	HIGH	LOW

BE - bit 7¶

Buffer Empty. This is set when the data word is transferred from the transmit buffer to the output shift register. It is cleared when the transmit buffer is reloaded by writing to the USART Data Register.

UE - bit 6¶

Underrun Error. This bit is set when the last word has been shifted out of the shift register before a new word has been loaded into the transmit buffer. It is cleared by either reading the TSR or by disabling the transmitter.

AT - bit 5¶

Auto Turnaround. Setting this bit enables the receiver at the end of the transmission of the last word in the transmitter, if the transmitter has been disabled. The bit is cleared at the end of the transmission.

END - bit 4¶

End. If the transmitter is disabled with a character still in the output shift register, transmission will continue until the character has been shifted out. Then this bit will be set. It is cleared by enabling the transmitter.

BREAK - bit 3¶

Break. Setting this bit will cause a break to be transmitted. Clearing the bit stops break transmission. The bit has no function in the synchronous mode. The Break bit cannot be set until the transmitter has been enabled and has had sufficient time for initialization (one clock cycle).

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HIGH/LOW - bits 2 and 1¶

High/low. These two bits select the form of transmitter output:

H	L	Output mode
0	0	Tri-state
0	1	Logical Low output
1	0	Logical High output
1	1	Loopback

In loopback mode the transmitter is connected to the receiver input and the transmitter clock (TC) is connected to the receiver clock (RC).

TE - bit 0: Transmitter Enable¶

This bit enables or disables the transmitter:

State	Function
0	Transmitter disable
1	Transmitter enable

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2.1.9 DIOC Interrupt System¶

The MC68020 has 8 interrupt levels. The standard DOMINO assignment of the levels is:

level	mnemonic	description
7	BFAIL	Power Fail
	LMPERR	Local Memory Parity Error
	OCINT7	OCTObus Stop Command
	PBTC	Test Connector
6	ASYL	Current loop I/O
5	ROR	OCTObus I/O
4		Reserved †
3		Reserved
2		MFP group interrupt
1		User applications
0		Idle

† used by DOMINO-MONITOR
MFP Multifunction Peripheral chip (68901)

Table 2. Standard interrupt level assignment for DOMINO I/O

All levels except level 2 are auto-vectored.

The interrupts are encoded as follows:

(BPFAIL + MPERR + OSTOP + PBTC) = INT7
ASYL = INT6
ROR = INT5

Figure 18. The interrupt system

Page 76¶

Interrupt level 7¶

7                            0
|  |  |  |  |  |  |  |  
INT7 source BERR   INTSOURCE register

FF8102 hex

The four most significant bits of the Interrupt Source (INTSOURCE) register represent the source level 7 interrupt. The four least significant bits indicate the source of a Bus Error. The INT7 source codes are:

bit	source	mnemonic
4	power fail	BPFAIL
5	local memory parity error	LMPERR
6	OCTObus INT7	OCINT7
7	test connector	PBTC

An interrupt on level 7 is pending until it is cleared i.e. until the INTSOURCE register is written to with a '1' corresponding to the bit set as an interrupt flag. The exception handler for level 7 interrupts gives BPFAIL the highest priority and PBTC the lowest.

INTSOURCE is reset by writing to the register with the corresponding bits set.

INTSOURCE must be cleared before an interrupt is serviced to allow other interrupts to occur on level 7.

BPFAIL¶

This interrupt will start the processor from EPROM after a power failure.

LMPERR¶

An error in the local DRAM causes an immediate switch to EPROM via this interrupt. The Master Control Register (MCR) is reset and all stacks are lost or invalid. A self-test routine checks to see the cause of the error and if:

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Chapter 2 The DOMINO Controller (DIOC)¶

a soft error - reloads from shared memory
a DRAM hardware error - switches to EPROM (shadow) mode

OCINT7

This interrupt occurs when the OCTObus generates an OCTObus stop message. The stop is issued when a DIOC fails to respond to any normal data path. An OCINT7 interrupt can be cleared by writing to the INT7 OCTObus Message Reset Register.

PBTC

This interrupt can be generated by the test connector when a DIOC does not respond to any of the normal data paths.

Interrupt level 6¶

An interrupt on this level is generated when:

a character is available in the input channel of the console (the ASYL channel).

OR

the output channel is ready to accept an output character.

The source of the interrupt is found by reading the receiver status register (RSR) of the MFP's USART.

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Chapter 2 The DOMINO Controller (DIOC)¶

Interrupt level 5¶

This interrupt occurs when either:

an OCTObus message is ready to be read

OR

the OBCON gate array is ready to transfer a new message

Interrupt level 4¶

This level is available to the user. The DOMINO-MONITOR stops at this level.

Interrupt level 3¶

Unused. Available to user.

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Chapter 2 The DOMINO Controller (DIOC)¶

Interrupt level 2¶

Interrupts on this level are generated by the Multifunction Peripheral (MFP) chip from a maximum of 16 sources. Each interrupt source has a unique interrupt vector which is passed to the microprocessor during the interrupt acknowledge cycle. The following devices generate interrupts:

internal timers
the USART (Universal Asynchronous Receiver/Transmitter) of the MFP
GPIP (General Purpose I/O register Port)

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Chapter 2 The DOMINO Controller (DIOC)¶

They are assigned to 16 MFP channels (bits 0-3 of the MFP interrupt vector register) as follows:

Bits	Channel name	Use
1 1 1 1	GPI 7 (I7)	Free
1 1 1 0	GPI 6 (I6)	Seek Interrupt
1 1 0 1	Timer A	RT-clock
1 1 0 0	Receive Buffer Full	Reserved/Not used
1 0 1 1	Receive Error	Receive Error
1 0 1 0	Transmit Buff.Empty	Reserved/Not used
1 0 0 1	Transmit Error	Transmit Error
1 0 0 0	Timer B	Free
0 1 1 1	GPI 5 (I5)	Disk Status interrupt
0 1 1 0	GPI 4 (I4)	DDC interrupt
0 1 0 1	Timer C	Free
0 1 0 0	Timer D	Baud rate generator
0 0 1 1	GPI 3 (I3)	DMA-trap interrupt
0 0 1 0	GPI 2 (I2)	EEPROM interrupt
0 0 0 1	GPI 1 (I1)	Free
0 0 0 0	GPI 0 (I0)	Free

Table 3. Standard Interrupts for MFP chip

Note: Channel 0000 has the lowest priority; channel 1111 the highest.

Interrupt level 1¶

The processor idles at this level.

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Chapter 2 The DOMINO Controller (DIOC)¶

2.1.10 Bus Error Operation¶

While an interrupt can only be served after the completion of the current instruction, the Bus Error (BERR) input signal to the MC68020 can abort a faulty bus cycle. A BERR will be reset immediately to avoid double bus faults.

7               0
|---------------|
| INT7 source  BERR |  INTSOURCE register
|---------------|

BERR can be asserted by the following sources, as indicated by bits 0-3 of the INTSOURCE register.

bit	source
0	protect trap
1	local timeout
2	MFbus timeout
3	BERR from test connector

protect trap
A BERR is generated and the bus cycle aborted if a protect violation occurs (protected memory address requested).

local timeout
This BERR occurs when either:

the on-board address is out of range (Address bit 31 = 0)

OR

DTACK (Data Acknowledge) is not returned to the processor by an accessed device.

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Chapter 2 The DOMINO Controller (DIOC)¶


MFbus timeout	This BERR occurs when an access of the MFbus Adapter (MFA) by the processor/DMA has timed out on the MFbus. The source of the interrupt can be read from the Read Status Register (RSR) of the MFP.
BERR	The BERR channel on the test connector can be driven by an external device to generate a BERR signal.

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Chapter 2 The DOMINO Controller (DIOC)¶

2.2 External DIOC control¶

The following processor functions are controlled by the external HALT and RESET signals:

start
stop
reset

HALT
This input signal to the MC68020 will, when asserted, cause the processor to stop at the end of the current bus cycle. Processing continues once the signal is not asserted. HALT is also generated internally by the processor when a serious hardware fault occurs (e.g. double bus fault).

RESET
This bi-directional signal allows the processor or an external device to initiate a system reset.

HALT and RESET operations¶

On a DIOC the HALT and RESET signal is controlled by four sources:

power failure
OCTObus commands
on-board reset switch
test connector

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Chapter 2 The DOMINO Controller (DIOC)¶

A power failure or depressing the reset switch will cause a total reset (assert both the HALT and RESET signals). The test connector and OCTObus commands can affect the signals individually. The test connector can be used, via the HALT signal, to drive the hardware in a single-step mode.

The signal logic for these signals is illustrated below:

Power Failure¶

MFbus control lines	BPFAIL
	BNAVAL

OCTObus Message¶

message decoder	RESET1
	IHALT

| push button | RES |

Logic Control¶

RESET and HALT control logic
- RESET = BPFAIL.BNAVAL+RESET1+RES
- HALT = IHALT

Figure 19. HALT and RESET selection

HALT and RESET are open-collector signals. The test connector accesses HALT and RESET directly. OCPALRES is used to reset hardware decoded messages on power-up, preventing illegal operations due to undefined signals.

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Chapter 2 The DOMINO Controller (DIOC)¶

Cold start detection¶

The circuit used to detect whether standby power was present during a power failure selects whether a cold or warm start is initiated. It generates the COLD signal used by MSR₁₀. The circuit is:

          LS00         LS00
RCOL      _______     _______
(MCR₁₀) |___|       |___|

BPFAIL₀    _______     _______
          |___|     |___| 

BTR₀       _______     _______         COLD(MSR₁₀)
          |___|     |___|

Figure 20. Power failure detection

The gates in this circuit must be supplied with standby power. BPFAIL and BTR are signals from the MFᵇᵘˢ.

BTR will be active when coming up from a cold start and will force COLD active. The processor will then read the MSR and reset it by setting RCOL (MCR₁₀). If a warm start is initiated (standby power had been present during the power failure), COLD remains inactive.

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Chapter 2 The DOMINO Controller (DIOC)¶

2.3 DIOC selftest¶

The DIOC will execute a selftest automatically after a cold start. The test can access local memory, registers and support circuitry but must not corrupt MFbus memory, peripheral devices or communication channels connected to the DIOC.

The selftest has two stages:

preboot
postboot

and takes a maximum of 3–4s.

preboot test¶

This test executes in PROM before booting. It tests the hardware needed to boot and run a program in RAM memory. The program is in assembly code and uses registers, not RAM, for variable data. The test sequence is:

PROM checksum
simple register test (MCR)
bus-error timeout test
RAM verify test 1
- find memory size
- address
- initialize memory
- data type on
parity test

postboot test¶

This test executes in RAM after booting. This test has no restrictions on memory use and is normally written in a high level language. The test is accessible via OPCOM on the ASYL/OCTObus.

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Chapter 2 The DOMINO Controller (DIOC)¶

The test sequence is:¶

RAM verify
- walking zero/one
MFP
register
interrupt
protect system
breakpoint
OBCON and BADAP
device-dependent

Error handling¶

Error information generated by the selftest routines can be monitored by:

looking at the test status on the test connector (using a logic analyser or LED-board)
looking for a lit red LED on the board edge
error messages output on the ASYL port
error messages sent over the OCTObus or in shared memory

Errors generated by the preboot test are monitored by an output routine to the ASYL port.

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Chapter 2 The DOMINO Controller (DIOC)¶

Test interface¶

The preboot test routines can only be used by the selftest. Other test routines can be invoked from both selftest and OPCOM.

User accessible tests¶

All tests except preboot can be started by the user (remote or local). Remote testing can be carried out by using the ASYL or OCTObus line to a host computer, while local tests can be run on a terminal hooked up to the ASYL port on the actual DIOC.

Error handling¶

Several levels of error information are available, depending upon where errors are detected. The levels are:

status information written to the test connector as the tests proceed
a lit red LED on the card edge indicating that the selftest routine has failed
error messages output to the ASYL port
error messages sent out over the OCTObus or to shared memory

Page 89¶

2.4 DIOC status¶

Three LEDs (Light Emitting Diodes) on the card denote the following status information:

LED colour	DIOC status
red	hardware fault
green	connect
yellow	running

LED colour (red green yellow)	DIOC activity
o x x	reset
o x .	preboot test/boot/postboot test
o o x	processor halt
x x .	ready to use
x o .	operative

o : on
x : off
. : flashing (see note)

Note: The yellow LED is connected to the address strobe (AS) of the microprocessor. Depending on microprocessor activity, the LED may be flashing so fast that it appears to be fully on.

Page 90¶

2.5 DIOC card design¶

The standard layout for all DIOC cards is:

Figure 21. Physical design of a DIOC

The signals on test connectors T1 and T2 are given in Appendix C.

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Chapter 3 The MFBus Adapter (MFA)¶

Page 92¶

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Chapter 3 The MFbus Adapter (MFA)¶

The MFbus adapter interfaces the DOMINO controllers to the MFbus.

This section describes the MFbus adapter interface of the DOMINO controller (DIOC) and includes how the MFA is programmed, as seen from the DIOC.

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Chapter 3 The MFbus ADAPTER (MFA)¶

The typical DOMINO environment for the MFA is illustrated below:

OCTObus

OCTObus ADAPTER (OBA)


*	*	*
CONSOLE	DOMINO Logic	M
and	* CPU part:	F
TRACE	- MC68020	b
Connector	- DRAM/EPROM/EEROM	u
	- RTC/Interrupt	s
*	- Memory Protect	A
	- MFP chip	D
D		A
E	Δ Device part:	P
V	- logic	T
I	- Request Arbiter	E
C		R
E		M
*	*	F
		A

: Standardized hardware design
Δ : Device-dependent hardware design
MFP : Multifunction Peripheral chip

Figure 22. A typical DOMINO design environment

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Chapter 3 The MFbus ADAPTER (MFA)¶

3.1 A functional overview of the MFbus Adapter (MFA)¶

The MFA is designed to simplify the DIOC design. It performs a number of MFbus related functions, hiding the MFbus details from the DIOC by:

taking care of all MFbus/DIOC timing
providing buffering to meet the load and drive specifications of the MFbus
address-limit checking
handling control cycles from the MFbus controller
generating the DIOC master/slave codes
checking and generating data parity
latching addresses onto the MFbus

The MFA consists of three functional blocks:

MFACT
control

MFA data bus (0-15)	ident	driver
MFAMF bus	MFAIL	MFADR

Figure 23. Functional block diagram of the MFbus Adapter

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Chapter 3 The MFbus ADAPTER (MFA)¶

Control block¶

This block controls communication between the MFbus and the DIOC. Its main units are the BADAP gate array and timing circuits.

Driver block¶

This block contains the drivers and receivers for the address and data bus. It also includes circuitry to check whether the address requested by the DIOC is within its access limits on the MFbus (this limit is held by the limit RAMs).

parity¶

The bus transceivers check and generate parity for data on the bus.

limit RAMs¶

These RAMs are written to by the MFbus controller when the MFbus system is initialized. They contain the MFbus address limits for the DIOC in the system. After MFbus initialization, they are enabled for read only. (see Section 3.5 on Write Limits.)

Ident block¶

This contains module type, model, ECO-level and the print version of the PCB. The ECO-level is encoded via straps on the PCB, the other values are hardwired in the print.

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Chapter 3 The MFbus ADAPTER (MFA)¶

3.2 MFA interface to DOMINO logic¶

The interface signals are:

MFbus adapter	DOMINO logic
16CLK
BDLAT	0
CERR	0
DAIN	1
DARY	1
DDRY	1
DONE	0
DTIM	0
DUADR	0
EDDAT	0
GNINC	1
NAVAL	1
PFAIL	0
TOTRES	0
DARQ	1
BYTE	0-3
CSBADAP
DDRQ	0
DLOCK	0
IA	2-30
DAD	0-1
MPERS	0
PROK	0
MFRW	1
BADRW	0
STOPDARQ
STRING	0
ID	0-31
DMB	0-7
	1

Figure 24. The MFA - DIOC logic interface

Page 98¶

Interface Signal Description¶

Signal	Description
16CLK	MFbus clock.
BDLAT₀	Bus Data Latch. When the DIOC is reading MFbus data, BDLAT tells the DIOC to latch the data present on the ID bus.
CERR₀	Cycle Error. An error occurred during the bus cycle. The source of the error can be found by reading the BADAP's device status register.
DAIN₁	Device Address Increment. Increment the address counter - used for string operations.
DARY₁	Device Address Ready. The address cycle has finished.
DDRY	Device Data Ready. The data cycle has finished.
DONE₀	String cycle is complete.
DTIM₀	Device Timeout. A DIOC timeout signal generated when the DARQ signal has been active too long, i.e. something is wrong with the address cycle.
DUADR₀	Disable Upper Address bytes. This disables the upper address word as the MFbus controller wants to write to the limit RAMs and needs part of the address bus (IA_16-31).
EDDAT₀	Enable Device Data. Enable DIOC onto the ID data bus.
GNINC₁	Generated Not Increment. This signal is generated by a BADAP register to tell the DIOC not to increment its address counters when the DAIN signal comes.
NAVAL₀	Not Available. The MFbus is unavailable (power failure).
PFAIL₀	Power Failure.

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Chapter 3 The MFbus ADAPTER (MFA)¶

Signal	Description
TOTRES₀	Total Reset. Standby power has disappeared and the system has to be restarted.
DARQ₁	Address Request. This DIOC request starts an address cycle on the MFbus if the address is valid i.e has passed the address check circuitry in the MFA.
BYTE_0-3	BYTE select for MFbus operation.
CSBADAP₀	Chip select for BADAP gate array.
DDRQ₀	Device Data Request. The DIOC starts a data cycle.
DLOCK₀	Device LOCK. This tells the MFA to tell MFbus controller that the DIOC wants the next MFbus cycle too.
IA_2-31	Internal Address bus. The main address bus between the DIOC and the MFA.
DAD_{1 0-1}	Address bits used when the DIOC accesses BADAP registers.
MPERS₀	Disables parity check on input data, and tells the MFbus that parity is not generated for output data.
PROK₁	Processor access OK. This tells the MFA that a string operation has been interrupted by a processor cycle.
MFRW₀	MFbus Read/Write signal from DIOC to MFA.
BADRW₀	BADAP Read/Write signal from DIOC to MFA.
STOPDARQ₀	This signal stops the DARQ from reaching the BADAP chip. It can be used for memory protection.
STRING₁	String access. This tells the MFA that a string access is taking place.
ID_{1 0-31}	Internal Data bus. Main data bus between the DIOC and MFA.

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Chapter 3 The MFbus ADAPTER (MFA)¶

MCD₁ 0-7

Data bus used when the DIOC accesses BADAP registers.

3.3 Signal Timing¶

The following illustrations are used in the timing diagrams:

---     ---     ---

   ________

---     ---     ---

This means that a signal can be either high or low at the specified time. The dashed lines indicate that the signal level does not matter, and the full lines say that the signal must have the correct level during that time.

________

This denotes a tri-state signal - a signal that can be either high or low at the specified time. The signal is enabled when there are two lines, and disabled when there is one line.

Note

These timing diagrams only show the order in which things occur. The timing is not to scale, µs and ns events are made the same size.

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Chapter 3 The MFbus ADAPTER (MFA)¶

Timing for MFbus access¶

| Signal   |  Timing  |
|----------|----------|
| DARQ₁    | Address  |
| DARY₁    |          |
| IA₁      |          |
| DLOCK₀   |          |
| MFRW₀    |          |
| DDRQ₀    | Data     |
| DDRY₀    |          |
| BYTE₀    |          |
| EDDAT₀   | Write    |
| ID₁      |          |
| BDLAT₀   | Read     |
| ID₁      |          |

Figure 25. MFbus timing (read, write, address, and data)

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Chapter 3 The MFbus ADAPTER (MFA)¶

Timing for string MFbus access¶

Signal	Description
DARQ₁
DARY₁
DDRQ₀
DDRY₀
DAIN₁
DONE₀

Figure 26. MFbus timing (string cycle)

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Chapter 3 The MFbus ADAPTER (MFA)¶

Timeout¶

Assuming a 4 MHz clock (timeout counter = 376₈ and Device Control Register ₃ = 0)

DARQ₁       |-----------------|                           timeout counter = 0
       t1   |                 |

16CLK  |--|--|--|--|--|--|--|--|--|--|--|--|--|--|
       |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
       |-|-|-|-|-|-|-|-|-|-|-|-|-|-|
                 t2

DTIM₀   |       |-----------------|                   

        t3      |                 |                  

DDRY₀   |-----------------------------------|-----------------|

CERR₀   |       |------------------------------------|
              Software
CSBADAP₀

time	from	until
t1	DARQ active	timeout	64µs
t2	timeout	error signals active	35ns
t3	timeout	DDRY low	1µs
t4	device status register read	CERR,DTIM,DDRY high	33ns

After timeout, DTIM and CERR go low and the BADAP will generate a fake DDRY-low to re-initiate. The error signals become inactive when.

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Chapter 3 The MFbus ADAPTER (MFA)¶

The Read Device Status register (RDS) is read by DIOC software (CSBADAP goes low).

Power failure¶

When a power failure is detected, PFAIL goes low followed by NAVAL approximately 10μs later. The DIOC should then be reset. Once power has returned, PFAIL goes high and, when the MFbus is ready for operation, NAVAL will also go high.

NAVAL   _____________
        │           │
PFAIL   _______|             |_________
              t1

Power is down
Bus unavailable
DIOC reset

t, PFAIL low to NAVAL ≈ 10 μs

In the future t will be increased to an order of ms so PFAIL can be used to interrupt the processor.

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Chapter 3 The MFbus ADAPTER (MFA)¶

3.4 MFA initialization and requests¶

MFA initialization¶

The MFA has to be initialized before it is ready to connect a DOMINO request to the MFB system.

This is done by the MFbus controller and is mandatory to all slots in a MFB system bank. The MFbus controller specifies:

the MFbus address area accessible to the DOMINO controller.
interleave mode (no, 2-, 4-, 8-way interleave)

The MFbus controller initialization of the MFbus adapter is dependent upon the adapter operation.

If an address issued with a request is outside its MFbus access range or the request channel to the MFbus controller is inhibited, a request can be ignored by the MFbus controller. The request will be timed out by the timer counter in the MFA and although a fatal system error occurs the DIOC is not blocked as all DIOCs have a general timeout for all processor cycles.

The typical user of the MFA timeout is a DMA request generated by an DMA controller with no internal timeouts.

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Chapter 3 The MFbus ADAPTER (MFA)¶

3.5 Programming the MFA by the MFbus controller¶

Each master (see chapter 4) connected to the MFbus should respond to the MFbus controller when accessed. The MFbus controller accesses a master with a MFbus control cycle (PIO). The cycle has the address format as follows:

BAxx:

17	13 12	7 6 5	0
Slot number	Module type	B	Register

BAxx
This is the bus address.

Slot no
This is the MFbus slot number in which the device is physically located.

Module type
This is the class of module that can be accessed in broadcast mode (i.e. if the B bit is set).

Register field
This field specifies which register (function) of the selected device is to be accessed. The following read/write registers are standard:

Register	Register function	Mnemonic
0	Read Module Type	RMT
1	Read Master Status	RMS
2	Read ECO level	RECOL
3	Read Device Status	RDS
0	Write Module Type	WMT
1	Write Master Control	WMC
2	Write OCTObus Initial values	WOI
3	Write Device Control	WDC
6	Write Limits	WLI

Table 4. Standard registers for MFbus communication

The bus read and write signal (BADRW) selects the type of register field.

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Chapter 3 The MFbus ADAPTER (MFA)¶

Read Module Type (RMT)¶

15	11 10	5 4 3	0
slot no.	module type	1	model

The MFbus reads the RMT of each slot during initialization. The register fields are:

slot no.
A 5-bit code permanently wired in the backwiring used by the MFbus Controller for control cycle (PIO) addressing.

module type
A 6-bit code indicating what kind of module is installed in the slot. It is hardwired on the printed circuit board (PCB).

model
A 4-bit code for special module types e.g. memory with different sizes of memory. It is normally hardwired on the PCB.

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Chapter 3 The MFbus ADAPTER (MFA)¶

Read Master Status (RMS)¶

15           8 7 6 5 4 3 2 1 0
+---------------------------------+
| not used | OE | DIS | DIB | PI | MB | EN |
+---------------------------------+

OE:
OCTObus Enable. When set, this bit indicates that the OBCON gate array has been initialized and is ready. The bit is a copy of WMC₇ (Write Master Control).

DIS:
Device Interleave Setting. These bits indicate the type of interleaving:

bit 6 5	interleave mode
0 0	none
0 1	2-way
1 1	4-way
1 1	8-way

They are copied from WMC_5-6.

DIB:
Device Interleave Bank. These two bits are used together with the DIS bits to indicate where the bank is in the interleave system. For example, if 2-way interleave is selected, DIB=0 will place equal addresses into this bank, DIB=1 will allow access for odd addresses.

PI:
Pirate. This indicates that the module is set up to pirate special addresses. It is a copy of WMC₂.

MB:
Mail Box. This bit can be written to by the local processor and read by the MFbus controller. It has been included in the design as a free bit and has no meaningful function as yet. Unfortunately, there is no free bit for a mailbox in the other direction, so any communication in that direction must be done via the OCTObus.

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Chapter 3 The MFbus ADAPTER (MFA)¶

EN:¶

Enable master request. This bit is cleared during initialization of a bank, it will be set when the bank is correctly configured and the bus is ready to use. It is a copy of WMC₀.

Read ECO Level (RECOL)¶

15	13 12	8 7	5 4 0
not used	print version	not used	ECO level

This register results in a read signal being generated by the BADAP. It can be used in a similar way to the RMT (Read Module Type) register. The ECO level of a board is set by straps on the board itself. (subject to change)

Read Device Status (RDS)¶

This register is used if an additional device status register (to the RMS) is needed.

Write Module Type (WMT)¶

15	8 7 6	5 0
not used	OSPED	module type

The module type read by the RMT command is written into the BADAP gate array by this command. It will also set the OCTObus speed (OSPED).

Page 110¶

Write Master Control (WMC)¶

15	8	7	6	5	4	3	2	1	0
not used	OE	DIS	DIB	PI	CD	EN

OE:¶

Octobus Enable. This controls the initialization of the OBCON gate array. OE is normally zero on power up and set to one by the MFbus controller.

DIS:¶

Device Interleave Setting. These two bits set the interleave mode as follows:

bit	interleave mode
6 5
0 0	none
0 1	2-way
1 1	4-way
1 1	8-way

DIB:¶

Device Interleave Bank. These two bits are used together with the DIS bits. They indicate where the bank is in the interleave system e.g. for a 2-way interleave, DIB=0 will make equal addresses enter this bank, and DIB=1 will allow access for odd addresses.

PI:¶

Pirate. This bit indicates that the module is set up to pirate special addresses.

CD:¶

Clear Device. This resets several flip-flops within the BADAP.

EN:¶

Enable master request. This bit cleared during initialization of a bank, and is set once the bank is correctly configured and the bus is ready for use.

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Chapter 3 The MFbus ADAPTER (MFA)¶

Write OCTObus Initialization Values (WOI)¶

7		2 1 0
STANO		PF

7		3 2 0
PF		BT

This 16-bit register has to be written to twice to load the complete OCTObus initialization values as the data path to the BADAP is only 8 bits wide.

STANO
This 5-bit field gives the OCTObus station number.

PF
This field gives the station number of the power failure handler. The field is split between the two bytes with the two most significant bits loaded with the OCTObus station number.

BT
This denotes the broadcast type of the DIOC.

Write Device Control (WDC)¶

This is a specially decoded register used in a similar way to RDS (Read Device Status). Present DIOC designs do not use this register.

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Chapter 3 The MFbus ADAPTER (MFA)¶

Write Limits (WLIM)¶

15		0
MFbus data	address within limit RAM

15	7	6	5	4	3	2	1	0
BADAP WMC	not used	OE	DIS	DIB	PI	CD	EN

Figure 27. Write limit RAM format

Limit RAMs¶

When the MFbus system is initialized by the MFbus controller, the limit RAMs are written to with the address limits of the DIOC in the MFbus address space.

After initialization the RAMs are enabled for read only (the "Write limit RAM latches" are disabled from the IA bus).

Addresses for MFbus accesses are sent on the IA bus to the limit RAMs. The RAMs then output the local and global data bits corresponding to the IA address. If a bit is set, the address is legal for local or global access, and the MFA starts an address cycle on the MFbus. (see Section 2.1.6.)

The MFbus writes to the limit RAMs on a DIOC by generating an MFbus address that writes to the particular DIOC and selects the write limit RAMs operation. This occupies the address bus so that the data lines are used as the limit RAM address (bits 16-31 on the physical bus). The data for the RAM (2 bits) is copied from the WMC register (DIS_0:1) during initialization, as during this time the DIS bits are not used and can be used for different functions until the MFbus is running.

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The 16-bit address and 2 bits of data give a resolution for the limit checking of 32 Kbytes over the full 2 Gbyte DIOC address range.

DISO
      ┌──────────────┐
      │ Limit        │
16-bit│ RAM          │────> MFA-DLOK
address│             │      (global)
      ├──────────────┤
      │ Limit        │────> MFA-DGOK
      │ RAM          │      (local)
      └──────────────┘
DIS1

Figure 28. Implementation of the limit RAM

The procedure for filling the limit RAMs is:

FOR address IN 0:65535 DO
    IF New Local Or Global Bit THEN
        Write Master Control Register
        (localBit, globalBit)
    ENDIF
    Write Limit RAMs (address)
ENDFOR

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3.6 Programming the MFA by the DOMINO processor¶

The MFA contains registers which can be programmed by the MC68020.

These registers are allocated an address range within the processor's I/O space, starting with the base address: FF8180 hex (see Section 2.1.6).

The registers are:

Address	Register
FF8180	Write Timeout Count
FF8182	Write Most significant String Count
FF8184	Write Least significant String Count
FF8186	Write Device Control
FF8180	Read Slot Number
FF8182	Read Most significant String Count
FF8184	Read Least significant String Count
FF8186	Read Device Status

Table 5. MFA internal register addresses

The Timeout Counter¶

The timeout counter starts counting when the BADAP is given an ARQ request and reloads the starting value when the request is removed.

The timeout counter is loaded with a value selected by the device and counts down at a rate of 4 MHz. This gives a maximum timeout of 64 μs ((256 x 1/(4*1000000)) x 1000000). If a longer timeout is required, bit 3 (TS) of the device control register can be set, so that the countdown frequency will be 250 kHz and the maximum timeout 1 ms.

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Chapter 3 The MFbus ADAPTER (MFA)¶

String Counter¶

The string counter is a 16-bit counter, loaded by two consecutive commands from the 8-bit bus (write most and least significant string count).

Note: Bit 0 (ST) in the device control register has to be set to enable a string mode access.

string mode¶

In string mode, the slave device is accessed by one address cycle only and receives a string of data cycles. The end of the data string is indicated by DONE going low. String cycles can be interrupted on the MFbus by the BEOSTR signal; the BADAP will resume by running a new address cycle before any subsequent data cycles are run.

Device Control Register¶

7	0
not used	CD TS DI MB ST

CD¶

Clear Device.

TS¶

Timeout Select (decrement rate). This sets the decrement frequency for the timeout counter.

TS	rate (MHz)
0	4.0
1	0.25

DI¶

Don't Increment the address in string mode.

MB¶

Mail Box.

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ST¶

STring mode. When this bit is set, the device is in string mode.

Slot Number¶

7	6	5	4		0
IL	TS	DI		slot number

slot number: This is slot number in which the device is located.
IL: InterLeave.
TS: Timeout Select (decrement rate).
DI: Don't Increment the address in string mode.

Read Status Register¶

7	6	5	4	3	2	1	0
BF	BE	PA	XP	AV	TO	NI	ST

BF: Bus Fatal error.
BE: Bus Error. A bus timeout.
PA: PArity error. Parity error on the MFbus.
XP: not used.
AV: Address Violation in string.
TO: TimeOut. A non-bus request timeout.

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NI	Not available or Inhibited.
ST	STring mode.

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Chapter 4: The Octobus Adapter (OBA)¶

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Chapter 4 The Octobus Adapter (OBA)¶

The OCTObus is an optimized bus for handling short messages used for synchronization of directly coupled processors.

The OCTObus plays an important role as the signalling bus in the multiprocessor configurations using DOMINO controllers and application processors.

In addition, it is used for initialization, maintenance and debugging and routing of error messages to a selected error handler.

An OCTObus Adapter (OBA) is implemented on the DIOC. Its design is centred upon the OBCON gate array chip.

A functional block-diagram of the OCTObus is given overleaf.

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

control
|<-------------------------------
OCTObus RDAT
TDAT --------------------------->|

Control	Receiver	Transmitter
*	path	path

initialization parameters of: - switches (masters) - BADAP (others)

Panel functions and interrupts to processor

: Implemented by the OBCON gate array
control : XREQ, XCLK and XRFO signals
RDAT ) RDAT and TDAT are the local OCTObus connections, they
TDAT ) are the differential signal XDAT on the global OCTObus

CMD Decode FIFO Power fail
--- processor databus ---

Figure 29. OCTObus implementation

4.1 The OCTObus protocol¶

OCTObus communication has the following features:

all nodes can gain control of the bus
any node can be a master
power failure is tolerated in all nodes
nodes can be physically removed from the bus
simple protocol allowing short interprocessor synchronization messages
retries handled by hardware

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

Each device connected to the OCTObus is an OCTObus node. Each node is connected via:

the global OCTObus (differential cable)
the local OCTObus (MFbus backwiring - TTL)

The cable is used to connect MFbus banks, ND-100 and ND-500 model II to the OCTObus, while the MFbus backwiring is used for devices located in an MFbus crate i.e. DOMINO controllers, ND-5000(s).

For the ND-100, the cable is connected to the MFbus linedriver; where an MFbus crate is used the cable is connected to the MFbus controller (this also links the bus into the MFbus backwiring).

The 4 differential signals are:

XREQ - Transmit request
XCLK - clock
XDAT - data
XRFO - Refresh oscillator

Data Rate¶

There is a trade-off between cable length and OCTObus speed. The table below gives the data rate for certain speed/distance combinations:

Cable length in m	Clock frequency in MHz	Net data rate in Mbits/s
6	4	1
60	1	250
120	0.5	125

Table 6. OCTObus data rate

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

A 1 MHz clock frequency is normally used, it is equivalent to a transmission time of 32µs per message.

4.2 OCTObus nodes and the MASTER¶

A maximum of 62 nodes can be addressed by one OCTObus. If more are required, the message protocol has a mechanism for 'bridging' to further OCTObuses.

One node must supply the OCTObus clock (XCLK) to the other nodes. This node is referred to as the OCTObus MASTER.

One node always operates as the MASTER. The MASTER indicates to all other nodes its presence by pulsing the OCTObus control lines (XRFO). If the pulse disappears a new MASTER will be automatically selected from the remaining operational nodes.

4.3 The OCTObus allocation algorithm¶

All nodes can try to gain control of the bus at any time.

A node that wants to send, issues a request (XREQ) which starts a burst of clock (XCLK) pulses from the MASTER.

When the pulse train starts, all requesting nodes start to transmit their message on the bus, but only as long as the XDAT line equals the bit-pattern sent by the node. The XDAT line is "wired-or" so that it will be "1" when at least one transmitter sends a "1". The format of an OCTObus frame ensures that sooner or later one and only one node is left as the transmitter on the bus. All others have to back-off and try again.

After successful transmission, a node will lose

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

Its priority. This ensures short access time for single-frame messages since transmitters with large messages are put at the end of the queue.

4.4 OCTObus frame format¶

An OCTObus message is 32 bits wide. It includes a 16-bit data unit which is supplied by the sender and read by the receiver.

← Direction of transmission.

32 31..............................1 0

 start              OCTObus frame               stop

Bit number in a OCTObus frame

30...27	26......21	20	19	18....13	12......5	4	3	2	1
Priority	Destination	C	B	Source	Information	Parity	Ack

..........data unit.........

Figure 30. OCTObus transmission frame

The signals transmitted during one frame are a Start and a Stop bit plus a 30-bit string composed of the fields shown in the figure above. The most significant bit, bit 31, is transmitted first.

The priority field is incremented each time the node has to back-off, retry, during the bus allocation. Several nodes may have the same number of retries and be sending to the same destination. In this case, the node with the lowest station number has priority. The priority

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

Counter can be set to its highest value for emergency messages e.g. power failure.

Priority¶

This 5-bit field contains the number of attempts made to transmit the frame (a 'last access counter').

Destination¶

This contains the address of the receiving node, the message destination.

If B=0 (normal transmission), this field contains one of 62 node numbers. (Node numbers 0 and 63 are illegal)

If B=1 (broadcast), this field contains one of six node types (see OCTObus Protocol Specification).

C¶

If C=1, the attached information is a control byte. The information field has special significance (see OCTObus Protocol Specification).

If C=0, the information field contains pure data, i.e "kick" information (see OCTObus Protocol Specification).

B¶

B=1 - Broadcast. All nodes of a specified type will accept this message.

B=0 - Normal transmission. Only the node with a matching destination number will accept this message.

Source¶

The unique address of transmitting node.

Information¶

The encoding of this byte depends upon the C bit (see OCTObus Protocol Specification).

Parity¶

Message parity code. The code is calculated by counting number of "1"s in the data unit and attaching the two least significant bits of the count to the message.

Ack¶

Acknowledgement of the frame. This is returned by the destination (receiving) node(s). The two bits are decoded as follows:

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

Ack	Normal transmission	Broadcast transmission
0 0	node not present	nodes not present
0 1	successful	successful
1 0	destination busy	destination busy
1 1	parity error	ambiguous response

Figure 31. The OCTObus acknowledge bits

Frame format as seen from OCTObus output driver¶

To send one byte of information, the format of the data written to the OCTObus interface is:

 15  14  13     8  7   0
| C | B | Dest/Type | Information |

Frame format as seen from OCTObus input driver¶

A received message has the format:

 15  14  13     8  7   0
| C | B | Source   | Information |

The Acknowledge field from the receiver¶

The Acknowledge bits are enabled onto the bus by the receiver as the two last bits of an OCTObus message. These two bits are coded to indicate to the transmitter whether the current message has been successfully received or not:

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

Ack	Normal transmission	no. of retries	Broadcast transmission	no. of retries
0 0	node not present	15	nodes not present	15
0 1	successful	-	successful	-
1 0	destination busy	255	destination busy	255
1 1	parity error	15	ambiguous response	0

Figure 32. The acknowledge bits and retries

The priority counter will be reset after each successful retransmission.

The number of retries can be specified in the OCTObus Transmitter Control Register. The table above gives the default and maximum number of retries. Reading the Transmit Status Register will tell you whether a message has been retransmitted or not.

4.5 Hardware-generated OCTObus messages¶

At power down/up a message is automatically transmitted by the OBCON gate array (OCTObus controller chip).

The power down/up message is a broadcast message to a selected type of nodes, defined as power failure recipients. The broadcast message recipients are defined during OCTObus initialization.

Only OCTObus nodes residing on the global OCTObus are allowed to send power down/up messages. OCTObus nodes residing on local OCTObus branches (i.e. in MFbus bank(s)) will also send hardware generated messages with the same format as the power fail message, but they mean "fatal controller hardware failure" rather than power fail. The difference is understood by the receiver, as it bases its interpretation of the message on the source of the transmitter.

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Power down/up messages received from nodes with station numbers 1 to 17 or less mean power fail, while the same message received from nodes with station numbers 20 to 76 do not.

The format of the power-down message is:

30......27 26........21 20 19 18....13 12.........5 4 3 2 1

| 1 1 1 1 | Destination | 1 | 1 | Source | 1 1 ... 1 1 | Parity | Ack |

Figure 33. The OCTObus power-down message format

The format of the power-up message is:

30......27 26........21 20 19 18....13 12.........5 4 3 2 1

| 1 1 1 1 | Destination | 1 | 1 | Source | 0 0 ... 0 0 | Parity | Ack |

Figure 34. The OCTObus power-up message format

The destination field contains the type of nodes that should accept the power up/down message.

4.6 Hardware-decoded messages¶

Some messages are decoded by hardware, i.e. they do not have to be read by software to affect the receiving node.

These messages control the OCTObus node processor, i.e. start/stop/reset etc. In addition, such messages force the node processor out of a hang situation by generating an interrupt on a non-maskable interrupt level. (Level 7 on the MC68020 processor.)

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The messages are:

Number	Name	Description
241	RESTART	Activates the RESET signal and restarts the controller after a total reset.
242	CONTINUE	Deactivates the HALT signal.
243	STOP	Activates the HALT signal. HALT must remain active until the CONTINUE message is received.
244	INT7	Generates a level 7 interrupt. The interrupt (OCINT7) can be stopped by software.
245	RESCOUNT	Resets the time reference counter.
376	POWERUP
377	POWERDOWN

Figure 35. The OCTObus hardware-decoded messages

4.7 INT7 OCTObus Message Reset Register¶

This register (OCINT7) contains no data bits. All accesses to the register (write only) will cause the INT7 OCTObus message to be inactive. The register has the DIOC processor address: FF810E.

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

4.8 OCTObus initialization and MASTER selection¶

The example below is of a system based on DOMINO controllers, application processors (ND-5000) implemented by two MFB crates and a ND-100.

Devices placed in MF'bus crate 0¶

MFB contr.	DIOC	DIOC	DIOC	ND-5000
Octo # 0	Octo **	Octo **	Octo **	Octo **

global OCTObus

local OCTObus

Devices placed in MF'bus crate 1¶

MFB contr.	DIOC	DIOC	DIOC	ND-5000
Octo # 0	Octo **	Octo **	Octo **	Octo **

to more MFbuses or other OCTObus nodes

# :thumbwheel switch
O :DIP switch
** :on-board programmable registers.

Figure 36. MFB system configuration

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

As shown in the figure, the DIOCs and application processors are connected together by an OCTObus. This bus is used to initialize the system and to synchronize the controllers.

The OCTObus can be divided into two parts:

local (MF'bus backwiring)
global (cable)

The global OCTObus connects the MF'buses and ND-100 together.

The local OCTObus connects the MFB controller to the nodes in the same crate.

The only difference between two parts is that nodes in local OCTObus can be logically removed from the OCTObus chain.

4.8.1 Initializing an OCTObus node¶

After a power up or RESET, the OCTObus has to be initialized before it can be used for message passing. All OCTObus nodes are assigned the following initial parameters:

a unique station
a broadcast type
the station for the power fail/fatal hardware handler
the OCTObus speed

The station number must be unique for each node in an OCTObus system.

The initial parameters of nodes residing on the global OCTObus are defined by thumbwheel switches i.e. the station number etc. is assigned manually. Local OCTObus nodes are

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

initialized by the MFbus controller with the parameters written into on-board registers.

The following rules apply when assigning the OCTObus station number.

all station numbers are octal
devices on the global OCTObus shall have numbers between 0₈ and 17₈ (hardwire the two upper bits to zero and use only one thumbwheel switch).
devices on the local OCTObus shall have numbers from 77₈ to 20₈ (downwards).

The initialization procedure has two phases:

phase I¶

This phase is executed automatically by the OCTObus.

All nodes on the global OCTObus are initialized, whilst all local OCTObus nodes are inhibited (awaiting initialization from their OCTObus representative, the MFbus controller).

The global nodes then select the MASTER node. Normally the node with the lowest station number is selected (usually the ND-100).

phase II¶

In this phase, the node (not necessarily the MASTER) which has been defined as the configurator, broadcasts the message "Identify yourself".

The only active nodes able to answer are those on the global OCTObus; which respond with their identification. The remaining nodes do not have station numbers and are inactive.

The configurator orders the MFB controller with the highest station number to configure its crate.

The MFB controller will read the RMT (module type) register for every slot in its crate,

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

using MFbus I/O cycles. An RMT of zero indicates an empty slot. Once it has determined which slots are being used, it will initialize those modules which are OCTObus nodes.

The MFB controller then sends the OCTObus message "Identify yourself" to station number 77₈. If there is no reply, the station is free and can be assigned to the nearest OCTObus node. If the station is in use, the MFB controller will repeat the same procedure until a free number is found. Once all the nodes in the crate have been numbered the MFB controller sends a "Finish" message to the configurator. The configurator then orders the MFB controller with the next highest station number to configure its crate. This sequence continues until all the MFB controllers are configured.

Station number assignment¶

Station numbers are assigned using two consecutive write operations to the < slot no. > + 10₈, i.e. the WOI register of the MFA is used (see Section 3.6).

The OCTObus node is started by writing "1" to bit 7 of MASTA at location 4₈ on the card (slot address + 4₈, as seen from MFB controller). Setting this bit generates the OBRES signal which will reset OBCON. The OCTObus node is now available and will answer when addressed. This same procedure is followed for all OCTObus nodes in the MFB crate. The MFB controller sends a "Finish" to the master telling the next MFB controller to configure its crate.

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

MFbus card crates¶

Two different crates are available:

1-bank 26 slots (one slot is not used)
2-bank 2 sets of 13 slots

Each slot in the crate has a unique number code identifying the slot position in the crate. In a 1-bank card rack, the modules are placed as follows:

-------------------- -------------------- -----------
| | | | | | | | | | | | | | | | | | | | | | | | | | |  
1  2 3 4                     17 18                     26
---------------------- -------------------- -----------

| | | | |--------------- |----------------------|---------------------| | not used | | | | Controller | port modules | memory modules | | module | memory modules | line driver modules | | | line driver modules | |

Figure 37. A 1-bank (26 slots) card crate

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Chapter 4 The OCTOBUS ADAPTER (OBA)¶

In a 2-bank crate (2 banks of 13 slots), the modules are placed as shown below:

|----|----|----|----|        |----|----|----|
|  1 |  2 |  3 |  4 | ....   | 24 | 25 | 26 |
|----|----|----|----|--------|----|----|----|
                          |  
|    port modules          |        port modules   |
|    memory modules        |        memory modules |
|    line driver modules   |        line driver modules |
|                          |
|      controller modules  |

Figure 38. A 2-bank (2 by 13 slot) card crate

The MFB controller will read from the nearest slot.

Slot Address Example¶

The slot address is calculated as follows:

Address 10₈, in slot number 14:

Convert slot number to octal: 14 = 16₈
Multiply by 2: 34₈
Add four zeros to find the slot address: 340000₈
Add the slot address as seen from MFB controller: 340000₈ + 10₈ = 340010₈

If the slot is empty, the RMT register will be zero hence, the corresponding address as seen from MFB controller will be:

Slot address + 0₈

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Appendix A: Glossary¶

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Appendix A Glossary¶

Term	Description
68901	The Multifunction Peripheral chip. This is the part number for the chip; it may be preceded by the manufacturer's identification, e.g. MC for Motorola.
BADAP	Gate array implementing some of the logic required by the MFbus Adapter (MFA).
DRAM	Dynamic Random Access Memory.
EEROM	Electrically Eraseable Read Only Memory.
hex	Hexadecimal notation of a number in base 16.
OBCON	Gate array implementing some of the logic required by the OCTObus Adapter (OBA).
octal	Base 8 representation of digits.

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Appendix B: Test Connector Pin-Outs¶

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Appendix B: Test Connector Pin-Outs¶

Test Connector I¶

PIN	A	B
1	D04	D05
2	D03	D06
3	D02	D07
4	D01	D08
5	D00	D09
6	AS*	D10
7	A0	D11
8	DS*	D12
9	R/W*	D13
10	reserved	D14
11	BG*	D15
12	BGACK*	GND
13	BR*	A23
14	+5V	A22
15	12CLK	A21
16	GND	+5V
17	HALT**	A20
18	RESET**	A19
19	reserved	A18
20	reserved	A17
21	reserved	A16
22	BERR**	A15
23	IPL2*	A14
24	IPL1*	A13
25	IPL0*	A12
26	FC2	A11
27	FC1	A10
28	FC0	A09
29	A01	A08
30	A02	A07
31	A03	A06
32	A04	A05

* active-low
** open-collector

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Appendix B Test Connector Pin-Outs¶

TEST-CONNECTOR II¶

PIN	A	B
1	I1+	I2-
2	O1+	O2-
3	A24	A25
4	A26	A27
5	A28	A29
6	A30	A31
7	GND	D16
8	D17	D18
9	D19	D20
10	D21	D22
11	D23	D24
12	D25	D26
13	D27	D28
14	D29	D30
15	D31	GND
16	SI20	DSACK0**
17	SI21	DSACK1**
18	DBEN*	ECS*
19	OCS*	RMC*
20	AVEC*	IPEND*
21	reserved	CDIS*
22	reserved	reserved
23	reserved	reserved
24	reserved	reserved
25	reserved	reserved
26	GND	GND
27	XCLK	XINT7*
28	ENTCO*	TPRES*
29	GND	GND
30	+5V	+5V
31	+5V	+5V
32	+5V	+5V

active-low
** open-collector

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Index¶

Term	Page(s)
* unused bit	41
68901	see Multifunction Peripheral chip (MFP) . . . 37
address decoding	24
hardware implementation	27
AER	40, 41, 50
ASYL	59, 61, 70-72
auto turnaround	57
BADAP	71, 80
BADRW	90
bank	89, 119
BERR	19, 28, 33, 60, 65
bootstrap	19
BPFAIL	19, 59, 60
break	57
break mode	20
breakpoint RAM	20
clearing	20
selection	20
BRKM	17
broadcast	110, 112
broadcast type	95, 116
buffer empty	57
buffer full	55
bus error	see BERR
operation	65
bus-error timeout test	70
COLD	18, 69
cold start	69
detection	117
configurator	8
context switching	80
control block	80

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Index¶

crate¶

1-bank ................................ 119
2-bank ................................ 120

data clock frequency¶

....................................... 53

data format¶

....................................... 54

DDR¶

....................................... 39, 40, 42

DIOC¶

standard layout ........................ 74
DIOC selftest .......................... 70
error handling ......................... 71
interface .............................. 72
DIOC status ............................ 73

DIS¶

........................................ 96

DMA request¶

........................................ 89

DOMINO I/O¶

typical configuration .................. 13

DOMINO-MONITOR¶

........................................ 8, 62

DOMINOS¶

........................................ 8

DRAM¶

........................................ 19
used as breakpoint ..................... 20

driver block¶

........................................ 80

DTACK¶

........................................ 65

ECO level¶

........................................ 93

ECO-level¶

........................................ 80

EOCR¶

........................................ 17

EPROM¶

........................................ 22
switching .............................. 19

frame error¶

........................................ 55

General Purpose I/O Registers¶

........................................ 41
AER .................................... 41
DDR .................................... 42
GPIP ................................... 41
global memory .......................... 24, 96
global OCTObus ........................ 107
GPIP ................................... 40, 41

HALT¶

........................................ 67

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Index¶

Topic	Page
I/O space address	25
device	27
EEPROM	25
system	25
tracer	27
IACK	39
Ident block	80
IEO	39
IERA	40, 43
IERB	40, 43
IMRA	40, 46
IMRB	40, 46
interleave	89
interleave mode	92, 94
Interrupt Control Registers	43
IERA	43
IERB	43
IMRA	46
IMRB	46
IPRA	44
IPRB	44
ISRA	45
ISRB	45
VR	46
interrupt level
1	64
2	63
3 and 2	62
4	62
5	62
6	61
7	60
interrupt levels	59
standard assignment	59
INTR	39
INTSOURCE	60, 65
INVP	17, 19
IPRA	40, 44
IPRB	40, 44
ISRA	40, 45
ISRB	40
LED1	17
LED2	17

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Index¶

limit checking resolution . . . 97
limit RAMs . . . 80, 96
- filling procedure . . . 97
LMPERR . . . 19, 59, 60
local memory . . . 24, 96
local OCTObus . . . 107
local timeout . . . 65
loopback mode . . . 58

Topic	Page(s)
mailbox	92
master	90
OCTObus node	108
Master Control Register (MCR)	16, 60
Master Status register (MSR)	18
MC68020	16
MCR	69
memory protection
- control	28
- global	28
- hardware	32
- local	28
memory switching	22

MFA¶

block diagram . . . 79
functions . . . 79
initialization . . . 89
interface . . . 81

MFA Registers¶

WDC . . . 95

MFA (processor registers)¶

Write Timeout Count . . . 98

MFA Registers¶

RDS . . . 90, 93
RECOL . . . 90, 93
RMS . . . 90, 92
RMT . . . 90, 91
WDC . . . 90
WLI . . . 90
WLIM . . . 96
WMC . . . 90, 94
WMT . . . 90, 93
WOI . . . 90, 95

MFbus¶

timeout . . . 87

MFbus Control Cycle (PIO)¶

. . . 90

MFbus Timeout¶

. . . 66

Page 151¶

Index¶

MFP¶

RESET ................................... 38
MFP chip timers ......................... 47
MFP control registers ................... 39
- list .................................. 40
MFP interrupt channel assignment ........ 64
MFP Timers .............................. 38
MFPR .................................... 17
module type ............................. 90, 91
MPER .................................... 17
MSR ..................................... 69
Multifunction Peripheral chip (MFP) ..... 37

NAVAL¶

......................................... 88

OBCON¶

......................................... 14, 62, 71, 92, 94, 118

OBRES¶

......................................... 118

OCINT7¶

......................................... 59, 61, 114

OCTObus¶

acknowledge bits ........................ 111
broadcast ............................... 110
configurator ............................ 117
enable .................................. 94
frame format ............................ 109
global .................................. 107, 112, 116
initialization .......................... 117
local ................................... 107, 112, 116
master .................................. 108
parity .................................. 110
priority ................................ 109
reset ................................... 34
speed ................................... 93, 107, 116
station number .......................... 95

OCTObus message¶

......................................... 62

ODIS¶

......................................... 17

OPCOM¶

......................................... 8, 70, 72

overrun ................................ 55

Parity¶

parity code ............................. 110
parity error ............................ 55
parity .................................. 19, 52, 54, 80

Page 152¶

Index¶

Term	Page(s)
parity mode	20
initialization	20
parity test	70
PBTC	59, 61
PFAIL	88
PIOCOS	8
postboot	70
power failure	88
recipients	112
preboot	70, 72
print version	80
PROM checksum	70
PROT	17, 28, 33
protect table	28
entry	30
initialization	31
protect trap	65
protection bits	30
protection level	29

Term	Page(s)
RAM verify test	70
RAMM	17
RCOL	17
RDS	93, 95
receiver error	55
RECOL	93
RESET	67
retry	109
RMS	92
RMT	91, 93, 118
ROR	18, 59
RSR	40, 55, 61

Term	Page(s)
SCR	40, 52
selftest	70
set breakpoint mode	20
SETB	17
SETP	17, 30, 33
slot number	90, 91
special module types	91
start/stop bits	54, 56
OCTObus frame	109

Page 153¶

Index¶

station number	95, 116
assignment	118
string counter	99
string cycle	86, 99
supervisor	29

TACR	40, 49
TADR	40, 48
TBCR	40, 49
TBDR	40, 48
TCCR	51
TCDCR	40
TCDR	40, 48
TDDR	40, 48
test connector	66
pin-outs	127

timeout¶

bus error	17, 70, 100
device	82
local	65
MFA	89
MFbus	65, 87
MFP timers	50
non-bus request	100
watchdog timer	34
timeout counter	98
timeout select	99, 100
timeout timing	87
Timer A,B mode	49
Timer C mode	51

Timer Control Registers¶

TACR	49
TBCR	49
TCCR	51

Timer Data Registers¶

TADR	48
TBDR	48
TCDR	48
TDDR	48

timing¶

MFbus access	85
string access	86
terminology	84
timeout	87

TPRES	18
tracer	9

Page 154¶

Index¶

Topic	Page
transmission length	53
transmitter output format	58
trigger condition	41
trigger mode	50
TSR	40, 57
UCR	40, 53
UDR	40
underrun	52, 57
USART	38
USART Registers
RSR	55
SCR	52
TSR	57
UCR	53
user	29
user accessible tests	72
Vector Register	45
VR	40, 46
warm start	69
watchdog timer	34
hardware	36
WDC	95
WLIM	96
WMC	92, 94, 96
WMT	93
WOI	95, 118

Page 155¶

UPDATING¶

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04/87	Version 1 EN

DOMINO Standard Hardware Description
Publ.No. ND-14.001.1 EN

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