Page 1¶

Test Micro Program Descriptions for ND-500¶

Page 2¶

Test Micro Program¶

Descriptions for¶

ND-500¶

Page 3¶

Notice¶

The information in this document is subject to change without notice. Norsk Data A.S assumes no responsibility for any errors that may appear in this document. Norsk Data A.S assumes no responsibility for the use or reliability of its software on equipment that is not furnished or supported by Norsk Data A.S.

The information described in this document is protected by copyright. It may not be photocopied, reproduced or translated without the prior consent of Norsk Data A.S.

Page 4¶

PRINTING RECORD¶

Printing	Notes
05/81	Version 01
09/81	Version 02

Test Micro Program Descriptions for ND-500
Publ. No. ND-30.013.02

NORSK DATA A.S
P.O. Box 4, Lindeberg gård
Oslo 10, Norway

Page 5¶

Manual Updates¶

Manuals can be updated in two ways, new versions and revisions. New versions consist of a complete new manual which replaces the old manual. New versions incorporate all revisions since the previous version. Revisions consist of one or more single pages to be merged into the manual by the user, each revised page being listed on the new printing record sent out with the revision. The old printing record should be replaced by the new one.

New versions and revisions are announced in the ND Bulletin and can be ordered as described below.

The reader's comments form at the back of this manual can be used both to report errors in the manual and to give an evaluation of the manual. Both detailed and general comments are welcome.

These forms, together with all types of inquiry and requests for documentation should be sent to the local ND office or (in Norway) to:

Documentation Department
Norsk Data A.S
P.O. Box 4, Lindeberg gård
Oslo 10

Page 6¶

PREFACE¶

THE PRODUCT¶

This manual describes the ND-500 micro test programs:

Program	Description
COMTE	ND-100/ND-500 communication test program
SLICE	ND-500 slice test program
MEMIC	ND-500 cache and memory test program
PREF	ND-500 prefetch processor test program
ARITH	ND-500 external arithmetic test program
NOMAN	ND-500 no-memory-management test program
QMOFF	ND-500 memory-management-off test program
QMENT	ND-500 memory-management-on test program
TRAPT	ND-500 trap system test program
EXTRA	Extra ND-500 test program

THE READER¶

This manual is mainly written for the ND-500 production and service staff.

PREREQUISITE KNOWLEDGE¶

NORD I/O SYSTEMS.

These programs may be run by persons without detailed knowledge of ND-500. If errors are reported, however, a good knowledge of ND-500 hardware is necessary in order to locate and repair the errors.

THE MANUAL¶

This manual describes how to load and start the test programs. Some useful information about ND-500 hardware (registers etc.) is also included. Each test program describes: - What the separate tests do, - Which break characters to use, - What the U-register contains.

ND - 30.013.02,

Page 7¶

ND-500 Reference Manual ND.05.009

Acknowledgement¶

The author is grateful for the willingness of the hardware chaps to supply the information necessary to the writing of this manual.

ND - 30.013.02

Page 8¶

TABLE OF CONTENTS¶

Section	Page
1. Introduction.	1
2. A list of some abbreviations that occur in the text.	3
3. A short list of registers, IOX instructions etc.	5
3.1. The CONTROL word register on 3022.	5
3.2. The STATUS register on 3022.	5
3.3. The memory address register (MAR) on 3022.	5
3.4. The DATA register on 3022.	6
3.5. The DATAX register on 3022.	6
3.6. The DATA-IN register on 5015.	6
3.7. The DATA-OUT register on 5015.	6
3.8. The BREAK register on 5015.	6
3.9. The write address register (WA) on 5015.	6
3.10. The lower and upper limit registers (LL, UL) on 3022.	7
3.11. The control register (CSCNT) on 5015.	7
3.12. The TAG-IN register on 5015 (I/O from ND-100).	7
3.13. The TAG-OUT register on 5015 (data from ND-500).	8
3.14. IOX instructions.	8
3.15. Some widely used communication subroutines.	9
3.15.1. Master clear, set stop bit, reset tag bits.	9
3.15.2. Write tag from the A register.	10
3.15.3. Write data to 5015 from the A register.	10
3.15.4. Read data from 5015 to the A register.	10
3.16. Subroutines to write and read the control store.	12
3.16.1. Write a 16-bit word into the control store.	12
3.16.2. Read a 16-bit word from the control store.	12
3.17. Other registers used by the test programs.	13

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Section¶

Section	Page
3.17.1. The prefetch status register (PSTAT, 32-bit, read only).	13
3.17.2. The (trap) status register S1.	15
3.17.3. The (trap) status register S2.	16
3.17.4. The memory and cache registers.	16
4.1. Data memory status registers (DST0, DSTS1, DSTS2).	17
4.2. Data memory control registers (DC0N0, DC0N1).	18
4.3. Instruction memory status registers (ISTS0, ISTS1, ISTS2).	18
4.4. Instruction memory control registers (IC0N0, IC0N1).	18
3.17.5. Memory modus register (MMOD).	18
3.17.6. Limit registers (HL,LL).	19
3.17.7. Memory management substitute registers.	19
3.17.8. Memory management registers.	20
8.1. Scratch files (ISCRF,DSCRF).	20
8.2. Status registers (IMSTS,DMSTS).	20
8.3. Logical address (IIADDR,DIADDR).	21
8.4. WIP/PGU broadside (IWPIGU,DWPIGU).	21
8.5. Real address (IRADDR,DRADDR).	21
8.6. Control registers (IMCNTR,DMCNTR).	21
8.7. Scratch file address (ISCFA,DSCFA).	22
8.8. Process control registers (IPROCC,DPROCC).	22
8.9. Domain registers (IDOMR,DDOMR).	22
8.10. Alternative domain registers (IADOM,DAD0M).	22
8.11. Current segment registers (ICSEG,DCSEG).	22
8.12. Alternative segment registers (IASG,DASEG).	22
8.13. Translate speed-up buffer page (ITSB,DTSB).	23
8.14. Sequential TSB address register (ISTS8,DSTS8).	23
8.15. Index for hashed or sequential TSB (IHXA,DHXA).	23

4. How to use the programs.¶

Section	Page
4.1. Stand-alone.	25
4.2. SINTRAN.	25
4.2.1. Loading.	25
4.2.2. Running one program at a time.	26
4.2.3. Running all programs in sequence.	26
4.3. Break characters.	27
4.4. The A (all) and O (one-by-one) mode.	28
4.5. The user register.	29
4.6. Recommended executing sequence.	29
4.7. Stop on full page.	29

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Section¶

	Page
5. The user micro program.	31
5.1. Description of the commands.	31
5.2. Some useful micro instructions.	33

6. COMTE - the ND-100/ND-500 communication test program.¶


6.1. General information.	35
6.2. How to load and start the program.	35
6.3. The test routines.	36
6.3.1. TST01 Continual master clear.	36
6.3.2. TST02 Set and reset stop bit.	36
6.3.3. TST03 Set and reset activate.	36
6.3.4. TST04 Set and reset reverse tag bus bit.	36
6.3.5. TST05 Test 3022 control register (bits 3-2 always 10).	36
6.3.6. TST06 Test 3022 status register.	37
6.3.7. TST07 Test 3022 memory address register.	37
6.3.8. TST08 Test 3022 data register.	37
6.3.9. TST09 Test 3022 lower limit register.	37
6.3.10. TST10 Test 3022 upper limit register.	37
6.3.11. TST11 Test tag dataway.	37
6.3.12. TST12 Test DATA-IN to DATA-OUT.	37
6.3.13. TST13 Test DATA-IN to WA-reg to DATA-OUT.	37
6.3.14. TST14 Test DATA-IN to BREAK-reg to DATA-OUT.	38
6.3.15. TST15 Test DATA-IN to CSCNT-reg to DATA-OUT.	38
6.3.16. TST16 Test TAG-OUT on 5015.	38
6.3.17. TST17 Test DATA-IN to DATA-OUT, most significant 16 bits.	38
6.3.18. TST18 Test control signals for load control store.	38
6.3.19. TST19 Test control signals for read control store.	38
6.3.20. TST20 Test write-and-read one 16-bit word in the control store.	39
6.3.21. TST21 Test control signals for start (from stop mode).	39
6.3.22. TST22 Test break (by setting WA=BREAK).	39

6.4. The verification routines.¶


6.4.1. TST23 Verify 3022 DATA register.	39
6.4.2. TST24 Verify 24 bits memory address register.	39
6.4.3. TST25 Verify 3022 CONTROL register (Bit 2=0. Bit 4=1 clears bit 6).	40

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Section¶

Section	Page
6.4.4. TST26 Verify STATUS register (not bits 0, 5, 011 and 017).	40
6.4.5. TST27 Verify 3022 (DMA) lower limit register.	40
6.4.6. TST28 Verify 3022 (DMA) upper limit register.	40
6.4.7. TST29 Verify tag dataway.	40
6.4.8. TST30 Verify dataway, least significant 16 bits.	40
6.4.9. TST31 Verify WA register.	41
6.4.10. TST32 Verify BREAK register.	41
6.4.11. TST33 Verify CSCNT register.	41
6.4.12. TST34 Verify TAG-OUT.	41
6.4.13. TST35 Verify data least significant 16 bits controlled by MOST bit.	41
6.4.14. TST36 Verify data most significant 16 bits controlled by MOST bit.	42
6.4.15. TST37 Verify control store.	42
6.4.16. TST38 Verify load of WA, BREAK, CONTROL, TAG-OUT, and read back a lot of times.	42
6.4.17. TST39 Verify DATA-IN to DATA-OUT, 32 bits.	42

6.5. The micro programmed routines.¶

Section	Page
6.5.1. TST40 Verify write-STATUS on 3022 from ND-500 (not bits 017, 011-7, 5, 0).	43
6.5.2. TST41 Verify write MAR on 3022 from ND-500.	43
6.5.3. TST42 Verify store-in-memory (write-DATA) from ND-500.	43
6.5.4. TST43 Verify read-and-write-STATUS on 3022 from ND-500 (not bits 017, 011-7, 5, 0).	44
6.5.5. TST44 Verify read-and-write-MAR on 3022 from ND-500.	44
6.5.6. TST45 Verify read-CONTROL-and-write-MAR on 3022 from ND-500 (not bits 6-3, always bit 2).	44
6.5.7. TST46 Verify read-and-write-DATA on 3022 from ND-500.	44
6.5.8. TST47 Verify DATA-IN to DATA-OUT, 32 bits, and then DATA-OUT-2 to DATA-OUT-1.	45
6.5.9. TST48 Verify lower and upper (DMA) limit registers during DMA transfer.	45
6.5.10. TST49 Micro programmed moving control store test.	45

7. SLICE - the ND-500 slice test program.¶

Section	Page
7.1. General information.	47
7.2. How to load and start the program.	47
7.3. The test routines.	47
7.3.1. TST01 Test single step.	47
7.4. The verification routines.	48
7.4.1. TST02 Verify sequencing (single step a lot of NEXT).	48

ND - 30.013.02

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Section¶

Section	Page
7.4.2. TST03 Verify sequencing (single step a lot of JMP *-1).	48
7.4.3. TST04 Verify sequencing (single step a lot of JSR SUB).	48
7.4.4. TST05 Verify sequencing (single step a lot of ALUJADIR and JMPCAR and W,XD).	49
7.4.5. TST06 Verify sequencing (single step a lot of ALUJADIR and JMPREL and NEXT).	49
7.4.6. TST07 Verify bit mask bits as A-opr and B-opr.	49
7.4.7. TST08 Verify AJBMR and BJBMR (bit mask register).	50
7.4.8. TST09 Verify all logical ALU functions.	50
7.4.9. TST10 Verify all arithmetical ALU functions.	50
7.4.10. TST11 Verify ND-500 registers (X#0-X#3, AM#0-AL#0-AM#1-AL#1, etc.).	51
7.4.11. TST12 Verify scratch registers as A-block and B-block.	51
7.4.12. TST13 Verify sequencing (conditional jumps).	51
7.4.13. TST14 Verify loop counter decrement (ICDECR).	52

8. MEMTC - the ND-500 cache and memory test program.¶

Section	Page
8.1. General information.	53
8.2. How to load and start the program.	53
8.3. The test routines.	56
8.3.1. TST01 Test EA (OPR(32-bits)-to-X#0-to-EA).	56
8.3.2. TST02 Test data/instr. memory (OPR(32-bits)-to-memory).	56
8.4. The verification routines.	56
8.4.1. TST03 Verify address arithmetic.	56
8.4.2. TST04 Verify data memory (address in address).	57
8.4.3. TST05 Verify data memory (compl. of address in address).	57
8.4.4. TST06 Verify instruction memory (address in address).	57
8.4.5. TST07 Verify instruction memory (compl. of address in address).	57
8.4.6. TST08 Verify memory (write once and read five times).	58
8.4.7. TST09 Verify data read and write with 1, 2, 3, and 4 bytes.	58
8.4.8. TST10 Verify data cache directory.	58
8.4.9. TST11 Verify instruction cache directory.	58

9. PREEF - the ND-500 prefetch processor test program.¶

	Page
	59

ND - 30.013.02

Page 13¶

Section¶

Section	Page
9.1. General information.	59
9.2. How to load and start the program.	59

9.3. The test routines.¶

| 9.3.1. TST01 Test prefetch clear and prefetch start. | 59 | | 9.3.2. TST02 Test prefetch clear, start, and continue. | 59 |

9.4. The verification routines.¶

| 9.4.1. TST03 Verify execution of instructions with no operands. | 60 | | 9.4.2. TST04 Verify execution of instructions without operands, with register number. | 60 | | 9.4.3. TST05 Verify execution of instructions with one operand. | 60 | | 9.4.4. TST06 Verify execution of GO:B. | 60 | | 9.4.5. TST07 Not yet implemented. | 61 | | 9.4.6. TST08 Verify execution of JMPMAP. | 61 |

10. ARITH - The ND-500 external arithmetic test program.¶

| | 63 |

10.1. General information.¶

| | 63 |

10.2. How to load and start the program.¶

| | 63 |

10.3. The test routines.¶

| 10.3.1. TST01 Test logical shift. | 63 | | 10.3.2. TST02 Test arithmetical shift. | 63 | | 10.3.3. TST03 Test rotational shift. | 63 | | 10.3.4. TST04 Test single floating sum (A+B). | 64 | | 10.3.5. TST05 Test single floating diff (A-B). | 64 | | 10.3.6. TST06 Test single floating mult (A*B). | 64 | | 10.3.7. TST07 Test single floating div (A/B). | 64 | | 10.3.8. TST08 Test convert to floating. | 64 | | 10.3.9. TST09 Test convert to integer. | 64 | | 10.3.10. TST10 Test single integer div (A/B). | 64 |

10.4. The verification routines.¶

| 10.4.1. TST11 Verify shift logical with shift count as argument. | 65 | | 10.4.2. TST12 Verify shift logical with shift count from shift count register. | 65 | | 10.4.3. TST13 Verify shift arithmetical with shift count as argument. | 65 | | 10.4.4. TST14 Verify shift arithmetical with shift count from shift count register. | 65 | | 10.4.5. TST15 Verify shift rotational with shift count as argument. | 65 | | 10.4.6. TST16 Verify shift rotational with shift count from shift count register. | 65 | | 10.4.7. TST17 Verify double floating sum. | 66 |

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Section¶

Section	Page
10.4.8. TST18 Verify double floating diff.	66
10.4.9. TST19 Verify double floating mult.	66
10.4.10. TST20 Verify double floating div.	66

11. NOMAN - the ND-500 no-memory-management test program.¶

67

11.1. General information.¶

67

11.2. How to load and start the program.¶

67

11.3. The test routines.¶

67

11.3.1. TST01 Test no-memory-management registers¶

67

11.4. The verification routines.¶

67

11.4.1. TST02 Verify DCINHL-DClNlHJ-DZPA-DUPL.¶

67

11.4.2. TST03 Verify ICINHLH-ICINHLJ-IZPA-IUPL.¶

67

11.4.3. TST04 Verify DRADDRM and DRADDRL.¶

68

11.4.4. TST05 Verify IRADDRM and IRADDRL.¶

68

11.4.5. TST06 Verify cache inhibit for data memory.¶

68

11.4.6. TST07 Verify cache inhibit for instruction memory.¶

68

11.4.7. TST08 Verify that read and write only affects the DZPA-DUPL area.¶

69

11.4.8. TST09 Verify that read and write only affects the IZPA-IUPL area.¶

69

11.4.9. TST10 Verify data cache clear.¶

69

11.4.10. TST11 Verify instruction cache clear.¶

69

12. GMOFF - the ND-500 memory-management-off test program.¶

71

12.1. General information.¶

71

12.2. How to load and start the program.¶

71

12.3. The test routines.¶

71

12.3.1. TST01 Not yet implemented.¶

71

12.3.2. TST02 Dump routine for IWTIPGU/DWIPGU.¶

71

12.4. The verification routines.¶

72

12.4.1. TST03 Verify data scratch file (DSCFA and DSCRF).¶

72

12.4.2. TST04 Verify instr. scratch file (ISCFA and ISCRF).¶

72

12.4.3. TST05 Verify DLADDR and DRADDR.¶

72

12.4.4. TST06 Verify ILADDR and IRADDR.¶

72

12.4.5. TST07 Verify WIP-buffer for data memory (DWIPGU).¶

72

12.4.6. TST08 Verify PGU-buffer for data memory (DWIPGU).¶

72

12.4.7. TST09 Verify WIP-buffer for instr. memory (IWIPGU).¶

72

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Section¶

Section	Page
12.4.8. TST10 Verify PGU-buffer for instr. memory (IWTIPGU).	73
12.4.9. TST11 Verify WIP and PGU for data memory write and read (HIC=1).	73
12.4.10. TST12 Verify WIP and PGU for instr. memory (HIC=1).	73

13. GMEMT - the ND-500 memory-management-on test program.¶

13.1. General information.¶

Page 75

13.2. How to load and start the program.¶

Page 75

13.3. The test routines.¶

13.3.1. TST01 Test hashed TSB.
- Page 75
13.3.2. TST02 Dump routine for IWMIPGU/DWMIPGU.
- Page 76
13.3.3. TST03 Test sequential TSB (hash index = 0).
- Page 76

13.4. The verification routines.¶

13.4.1. TST04 Verify the hash addressed TSB for data memory (DTSB).
- Page 77
13.4.2. TST05 Verify the hash addressed TSB for instr. memory (ITSB).
- Page 77
13.4.3. TST06 Verify the sequential addressed TSB for data memory (DTSB).
- Page 77
13.4.4. TST07 Verify the sequential addressed TSB for instr. memory (ITSB).
- Page 78
13.4.5. TST08 Verify data cache clear.
- Page 78
13.4.6. TST09 Verify instr. cache clear.
- Page 78

14. TRAPT - the ND-500 trap system test program.¶

14.1. General information.¶

Page 79

14.2. How to load and start the program.¶

Page 79

14.3. The test routines.¶

14.3.1. TST01 Not yet implemented.
- Page 79
14.3.2. TST02 Not yet implemented.
- Page 79

14.4. The verification routines.¶

14.4.1. TST03 Verify S1 traps enabled by the TE register.
- Page 79
14.4.2. TST04 Verify S1 traps not enabled by the TE register.
- Page 80
14.4.3. TST05 Verify S2 traps.
- Page 80
14.4.4. TST06 Verify S1 bit 5 and 6 (zero and carry, integer arithmetic).
- Page 80
14.4.5. TST07 Verify S1 bit 5 (zero, floating

ND - 30.013.02

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Section¶

		Page
arithmetic).		80
14.4.6.	TST08 Verify S1 bit 6 and 011 (carry and overflow).	80
14.4.7.	TST09 Verify S1 bit 7 (sign, integer arithmetic).	80
14.4.8.	TST10 Verify S1 bit 7 (sign, floating arithmetic).	80
14.4.9.	TST11 Verify S1 bit 010 and 6 and 5 (flag and carry and zero).	81
14.4.10.	TST12 Verify overflow trap (S1 bit 011).	81
14.4.11.	TST13 Verify floating underflow trap (S1 bit 015).	81
14.4.12.	TST14 Verify floating overflow trap (S1 bit 016).	81
14.4.13.	TST15 Verify single instruction trap (S1 bit 021).	81
14.4.14.	TST16 Verify branch trap (S1 bit 022).	81
14.4.15.	TST17 Verify address trap fetch (S1 bit 025).	82
14.4.16.	TST18 Verify address trap read for data memory (S1 bit 026).	82
14.4.17.	TST19 Verify address trap write for data memory (S1 bit 027).	82
14.4.18.	TST20 Verify address zero access trap for instruction fetch (S1 bit 030).	82
14.4.19.	TST21 Verify address zero access trap for data memory (S1 bit 030).	83
14.4.20.	TST22 Verify disable process switch timeout (S1 bit 036).	83
14.4.21.	TST23 Verify disable process switch error (S1 bit 037).	83
14.4.22.	TST24 Verify index scaling error trap (S2 bit 0).	83
14.4.23.	TST25 Verify illegal instruction code trap (S2 bit 1).	83
14.4.24.	TST26 Verify illegal operand specifier trap (S2 bit 2).	83
14.4.25.	TST27 Verify activate-from-ND-100 trap (S2 bit 5).	84
14.4.26.	TST28 Verify terminate-from-ND-100 trap (S2 bit 6).	84
14.4.27.	TST29 Verify IFAIL trap (S2 bit 010).	84
14.4.28.	TST30 Verify DFAIL trap (S2 bit 011).	84
14.4.29.	TST31 Verify processor fault trap (S2 bit 013).	84

15. FXTRA - the ND-500 extra test program.¶

15.1. General information.¶

85

15.2. How to load and start the program.¶

85

15.3. The test routines.¶

85

15.3.1. TST01 Not yet implemented.¶

85

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Page 17¶

Section¶

Section	Page
15.4. The verification routines.	85
15.4.1. TST02 Verify index counters.	85
15.4.2. TST03 Verify conversion (BYTH BYTW HWTW).	85
15.4.3. TST04 Verify conditional ALU.	86
15.4.4. TST05 Verify prefetch addressing modes.	86
15.4.5. TST06 Verify W1:=DESC(L.0110:B)(R4).	86
15.4.6. TST07 Verify INIT, CALL, ENTS, RET.	87

Appendix A¶

ND-500 micro mnemonics in alphabetical and numerical order 89

Index¶

119

ND - 30.013.02

Page 18¶

Introduction¶

1. Introduction¶

The micro test programs test the ND-500 by executing IOX-instructions. They do not use the interrupt system.

The micro test programs work in two ways: - They test the communication interfaces (3022, 5015) by executing IOX-instructions from the ND-100 (ND-500 is passive). In this way, the first testing of the ND-100/ND-500 communication is done. - They test ND-500 by loading small micro programs into the control store, starting them, and checking the results. These micro programs are always loaded from the specified minimum control store address. Utility micro programs, like dump programs, initiation programs, etc., are loaded into the uppermost part of the control store. The micro programs are relocatable.

The programs consist of sets of subroutines, each testing a small part of ND-500. There are two different kinds of subroutines: - Verification routines that run tests, check results, and report errors, if any. - Test routines, intended to run repeatedly and to be used together with oscilloscopes, logic probes, etc., to locate errors. As input to these routines there is a simulated OPR, with the possibility to flip (change from 0 to 1 to 0 to 1 ...) any of the bits in it.

Each program may run in one-by-one-mode (one routine runs over and over again), or in all-mode where all routines are run in sequence, one after another.

All the programs may also be run in sequence (one after another). This is intended for week-end runs, for instance. The programs may be started friday nights, and the results collected monday morning.

The error messages are assumed to be self-explanatory.

| ND - 30.013.02 |

Page 19¶

Introduction¶

ND - 30.013.02

Page 20¶

A list of some abbreviations that occur in the text¶

2. A list of some abbreviations that occur in the text¶

Some of the abbreviations are micro code mnemonics and should be looked for in the mnemonics list.

Abbreviation	Description
ALT	Alternative addressing mode.
BDU	Data bus on the 3022 card.
CDB	Internal bus for the ND-500 CPU cards.
DBU	A bus between the 3022 card and the 5015 card.
DOUB	Data bus on the 3022 card.
DUEN	A decoded value in the TAGIN register on the 5015 card. It enables the least significant part of the DATA-OUT register (IODOUT).
DUT	A bus on the 5015 card.
MM	Memory Management system.
MOST	Bit 7 in the TAGOUT register on the 5015 card. Will select the most or the least significant part of some 32 bit registers.
OPR	Operator register. Will be displayed on the ND-100 front panel if the user types U/2F cr on terminal 1 when this is in monitor mode. It is used by most routines to display test information.
TE	Trap enable register.
TSB	Translation Speedup Buffer. Belongs to the memory management system.
WA	Write Address register on the 5015 card. It holds a control store address.

Page 21¶

Abbreviations¶

A list of some abbreviations that occur in the text.

Page 22¶

A short list of registers, IOX instructions etc.¶

The interface between the ND-100 and the ND-500 consists of 2 interface cards; the 3022 card on the ND-100, and the 5015 card on the ND-500. These cards contain several registers, which are listed below.

3.1. The CONTROL word register on 3022.¶

Bit	Meaning
0	Enable interrupt from ND-500
1	Not used
2	Activate ND-500 operation (and lock the communication)
3	Test mode
4	ND-500 programmed clear
5	Disable TAG-IN decoding when locked
6	DMA error
7	Command chaining
8-14	ND-500 operation
15	Not used

3.2. The STATUS register on 3022.¶

Bit	Meaning
0	Interrupt enabled
1	Not used
2	ND-500 busy
3	ND-500 finished
4	Error
5	Interface locked
6	DMA error
7	ND-500 power fault (set by micro program). The stop bit is set
8	ND-500 power is/has been off
9	ND-500 micro clock has stopped
10-14	ND-500 stop reason
15	CONTROL register bit 15

3.3. The memory address register (MAR) on 3022.¶

This is a 24-bit register, pointing to the ND-100 memory. It is used in DMA transfers. It must be loaded from the 16-bit A-register in two operations. The most significant part is loaded first. It must also be read in two operations. The least significant part will be read first. When it is read, the upper half of the leftmost 16 bits of MAR (bits 24-31, not used) will be equal to the upper half of the rightmost 16 bits (bits 8-15).

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3.4. The DATA register on 3022.¶

This is a 16 bit register. It acts as an intermediary between the ND-500 and the ND-100 memory in DMA transfers from ND-500 to ND-100. In DMA transfers from ND-100 to ND-500, the DATAX register is used as the intermediary register, but the DATA register is set, nonetheless.

3.5. The DATAX register on 3022.¶

This 16-bit register connects the bus DOUB with the bus BOU. It is also used in DMA transfers from ND-100 to ND-500. Do not confuse it with the DATA register.

3.6. The DATA-IN register on 5015.¶

This 32-bit register is either used as a whole, or as DATA-IN-1 (the lower 16 bits), and DATA-IN-2 (the uppermost 16 bits). When the other registers on the 5015 cards are loaded from ND-100, data goes via the DATA-IN register to the CDB bus. In DMA read (ND-100 memory read by ND-500), data will go to the DATA-IN register. The MOST bit selects the most or least significant part.

3.7. The DATA-OUT register on 5015.¶

This 32-bit register is either used as a whole, or as DATA-OUT-1 (the lower 16 bits), and DATA-OUT-2 (the uppermost 16 bits). When the other registers on 5015 are read from ND-100, data goes via DATA-OUT to ND-100. In DMA write (ND-500 to ND-100), data must be placed in DATA-OUT before the write. The MOST bit selects the most or least significant part.

3.8. The BREAK register on 5015.¶

This 16-bit register is used when the control store is loaded. Data to be loaded must be in the BREAK register. The BREAK register is connected to the least significant part of the CDB bus.

3.9. The write address register (WA) on 5015.¶

The 16-bit WA register is used to hold the control store address when loading and reading the control store. The WA register is connected to the least significant part of the CDB bus.

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A short list of registers, IOX instructions etc.¶

3.10. The lower and upper limit registers (LL, UL) on 3022.¶

These are 16-bit registers, and represent bits 8-23 of a DMA address. They are compared with bits 8-23 of the MAR register to ensure that ND-500 keeps within limits. For instance, if LL contains 1, and UL contains 3, the legal area for DMA transfers is 0400, 0401, ..., 01376, and 01377.

3.11. The control register (CSCNT) on 5015.¶

Bit	Name	Meaning
0	CSLOAD	Control store load
1	CSREAD	Control store read
2-5	WE0,WE1,WE2,WE3	Control store group (0-8)
6	BRKEN	BREAK enable
7	STADREN	Start address enable
8	TSTPTTY	Test control-store-parity-checking (ND-500 passive)
9	TSTTIQ	Returns TAG-OUT instead of TAG-IN
10	CSPTY	Control store parity
11	AFIN	Prefetch addr. calc. not finished
12	PFIN	Prefetch instruction not finished
13	BALM	Memory reference not finished
14-15		Not used

Bits 10-15 may only be read. They give micro program stop conditions.

3.12. The TAG-IN register on 5015 (I/O from ND-100).¶

The tag registers are additional control registers used to control the communication. Bits 0-3 in the TAG-IN register on 5015 give 16 code values. Bit 4 is not used, and bit 5 (octal 040) is used to return TAG-IN bits (0-4). The codes are:

Bit	Name	Meaning
0		Not used
1	DICLKl	Clock DATA-IN-1 register
2	DICLK2	Clock DATA-IN-2 register
3	DUCLK	Clock DATA-OUT register (both)
4	WAeLK	Clock write-addr register
5	BRKCLK	Clock BREAK register
6	TGUCUIK	Clock TAG-OUT register
7	CNICLK	Clock CSCNT register
8	DlEN	Enable DATA-IN register to bus (CDB)
9	DUEN	Enable DATA-OUT register (least sign.)
10	WAR	Read write-addr register
11	BRKR	Read BREAK register
12	CNTR	Read CSCNT register
13	RESBRK	Reset break
14	DUNI	Unlock
15	EOUTEN	Enable data line driver (from ND-500)

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A Short List of Registers, IOX Instructions Etc.¶

3.13. The TAG-OUT Register on 5015 (Data from ND-500).¶

Bits 0-2 in the TAG-OUT register on 5015 give 8 code values.
Bit 3 means ND-100 if it is 0, and not ND-100 if it is 1.
Bits 4-6 are not used.
Bit 7 is the MOST bit. It enables the most significant part of the DATA-OUT register, and determines which part of the register to use when micro-programmed. MOST also controls least/most significant part of the DATA-IN register. The codes are (for MOST=1, add 0200):

Bit	Meaning
0	Read memory address register
1	Write memory address register
2	Read STATUS register
3	Write STATUS register
4	Read CONTROL register
5	Reset activate
6	Read DATA register (and ND-100 memory)
7	Write DATA register (and then into ND-100 memory)

3.14. IOX Instructions.¶

The ND-500 communication can be locked or unlocked, in test mode or not in test mode. These states are set by IOX ICON (load CONTROL register). IOX instructions have different meanings, depending on the state. In the following list, the three columns display the MAC mnemonics of physical device numbers, the octal device numbers themselves, and their meaning.

Locked and Not in Test Mode:¶

Mnemonic	Octal	Meaning
RSTA	062	Read STATUS register
MCLR	066	ND-500 Master Clear
TERM	067	Terminate
RTAG	070	Read TAG-IN
WTAG	071	Write TAG-OUT
WDAT	073	Write DATAX (NB not the DATA register)
SLOC	074	Set locked
CLKD	075	Clock DATA
UNLC	076	Release locked (unlock)
RETG	077	Return tag

Locked and In Test Mode:¶

Mnemonic	Octal	Meaning
RSTA	062	Read STATUS register
RCON	064	Read CONTROL register

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Unlocked and not in test mode:¶

Code	Description
RMAR 060	Read memory address register
LMAR 061	Load memory address register
RSTA 062	Read STATUS register
LCON 065	Load CONTROL register
MCLR 066	ND-500 Master Clear
TERM 067	Terminate
RTAG 070	Read TAG-IN
WTAG 071	Write TAG-OUT
WDAT 073	Write DATAX (NB not the DATA register)
SLOC 074	Set locked
UNLC 076	Release locked (unlock)
RETG 077	Return tag

Unlocked and in test mode:¶

Code	Description
RMAR 060	Read memory address register (do it twice)
LMAR 061	Load memory address register (do it twice)
RSTA 062	Read STATUS register
LSTA 063	Load STATUS register
RCON 064	Read CONTROL register
LCON 065	Load CONTROL register
MCLR 066	Load DATA register
TERM 067	Load DATA register
RTAG 070	Load upper limit register
WTAG 071	Load upper limit register
RLOW 072	Read lower limit register
WDAT 073	Load lower limit register

ND-100 bits 0-15 go to limit register bits 8-23.

3.15. Some widely used communication subroutines.¶

The routines that follow below are written in MAC (assembly) code.

3.15.1. Master clear, set stop bit, reset tag bits.¶

IOX UNLC   % unlock
SAA 040
IOX LCON
SAA 2
IOX RETG   % set stop bit
IOX MCLR
SAA 0
IOX WTAG   % write TAG-OUT on 3022
SAA 044
IOX LCON   % activate
IOX UNLC
SAA 040
IOX LCON   % reset activate
EXIT

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3.15.2. Write tag from the A register.¶

IOX WTAG  % write TAG-out on 3022
SAA 044
IOX LCON  % activate
IOX UNLC
SAA 040
IOX LCON  % reset activate
EXIT

3.15.3. Write data to 5015 from the A register.¶

The following routine uses the most/least significant part of the DATA-IN register, depending on the value of n (DATA-IN-1 is the least significant part):

IOX WDAT  % A register to DATAX
SAA n     % n=1: clock DATA-IN-1. n=2: clock DATA-IN-2
IOX WTAG
SAA 044
IOX LCON  % activate
IOX UNLC
SAA 040
IOX LCON  % reset activate
SAA 010   % enable DATA-IN to the CDB bus on 5015
IOX WTAG
SAA 044
IOX LCON  % activate
IOX UNLC
SAA 040
IOX LCON  % reset activate
EXIT

3.15.4. Read data from 5015 to the A register.¶

The following routine has 3 entry points. The first does not enable the DATA-OUT register (DUEN). The third does not clock the CDB bus to the DATA-OUT register.

ENTRY1=*

SAA 3
IOX WTAG  % clock CDB to DATA-OUT
SAA 044
IOX LCON  % activate
IOX UNLC
SAA 040
IOX LCON  % reset activate
JMP COMON

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ENTR2=*¶

SAA 3
IOX WTAG % clock CDB to DATA-OUT
SAA 044
IOX LCON % activate
IOX UNLC
SAA 040
IOX LCON % reset activate

ENTR3=*¶

SAA 011
IOX WTAG % enable DATA-OUT
SAA 044
IOX LCON % activate
IOX UNLC
SAA 040
IOX LCON % reset activate

COMON=*¶

SAA 017
IOX WTAG % enable data line driver (DUT to DBU)
SAA 044
IOX LCON % activate
IOX CLKD % clock DATA on 3022
IOX UNLC
SAA 050
IOX LCON % set test mode
SAA 0
IOX MCLR % read DATA (test mode)
STA SAVE
SAA 040
IOX LCON
SAA 0
IOX WTAG % reset tag bits
SAA 044
IOX LCON
IOX UNLC
SAA 040
IOX LCON % reset activate
LDA SAVE
EXIT

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A Short List of Registers, IOX Instructions Etc.¶

3.16. Subroutines to Write and Read the Control Store¶

The control store address is supposed to be in the WA register. The part number is a number in the range 0-010. A control store word consists of 9 16-bit words, and the part number points to one of these 9 words. Part number 010 (8) points to the most significant part. Data to be written must be in the BREAK register. Data that is read will appear in DATA-OUT-l. The WA register is set by the sequence

LDA ADDR; JPL WRDAT; SAA 4; JPL WRTAG

3.16.1. Write a 16-bit Word into the Control Store¶

The A register contains the 16 bit data word. The T register contains a control word that is 1, 5, 011, 015, ..., 041 depending on the part number (0-010).

STA SAVE
COPY SL DA
STA LINK
LDA SAVE
JPL WRDAT  % data to the CDB bus on 5015
SAA 5
JPL WRTAG % clock the BREAK register
COPY ST DA
JPL WRDAT % control word to the CDB bus
SAA 7
JPL WRTAG % clock the CSCNT register
LDA SAVE
JMP I LINK

3.16.2. Read a 16-bit Word from the Control Store¶

The A register contains a control word that is 2, 6, 012, 016, ..., 042 depending on the part number (0-010).

STA SAVE
COPY SL DA
STA LINK
LDA SAVE
JPL WRDAT % control word to the CDB bus
SAA 7
JPL WRTAG % clock the CSCNT register
JPL ENIR3 % read data, already in DATA-OUT
JMP I LINK

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A short list of registers, IOX instructions etc.¶

3.17. Other registers used by the test programs.¶

3.17.1. The prefetch status register (PSTAT, 32-bit, read only).¶

Bits	Name	Meaning
0-10	EP	Operation code.
		Bit 10 is 0: short operation code. Bits 8-9 are then both zero. Bits 0-7 contain 252 different operation codes, complemented, and not 256. The codes 111111xx, where x is 1 or 0, do not exist for short codes. When the six most significant bits are one, it means long operation code.
		Bit 10 is 1: long operation code. Bits 0-9 contain 1024 different operation codes, complemented. A long operation code consists of 16 bits. The six most significant bits are 1, and, since EP is 11 bits long, 5 of them are discarded.
11-14	PCD	Program counter displacement. Gives the length (complemented) of the current instruction. 017 means 1 byte, 016 2 bytes, and so on.
15-16	VLB	Valid bytes. 3 means 4 bytes left in the instruction buffer, 2 means 3 bytes left, and so on.
17-19	OPTYP	Operand type. From 0 to 5: word, float, halfword, byte, bit, and double float.
20	REGOP	Register operand. 1 if the address code (first byte of operand specifier) was 0320-0323, otherwise 0.
21	CONOP	Constant operand. 1 for constant operands as, for instance, in argument instructions, otherwise 0.

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Bit	Name	Description
22	DESC	Descriptor addressing. 0 if legal, otherwise 1.
23	WR	Write operation. 1 if write operation, otherwise 0.
24		Not used.
25	PFIRST	First operand. 1 for the first operand, otherwise 0. Becomes 0 as soon as the first operand has been fetched. For a sequence of LDR instructions, for instance, it will be 1 all the time.
26-27	DX	Descriptor register. Used in descriptor addressing to give the number of the register to use. 3 means R1, 2 means R2, 1 means R3, and 0 means R4.
28-29	SXSEL	Source register select. Gives the number of the source register, when there is one. 3 means R1, and so on.
30-31	DXSEL	Destination register select. Gives the number of the destination register, when there is one. 3 means R1, and so on.

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3.17.2. The (trap) status register S1.¶

This is a 32 bit register. Only bits 9-31 can give a trap. If one of bits 9-29 is to give a trap, the corresponding bit must be set in the trap enable (TE) register.

Bit	Meaning
0	Not used
1	Privileged instruction allowed
2	Part done
3	Instruction reference
4	Process switch disable
5	Zero
6	Carry
7	Sign
8	Flag
9	Overflow
10	Not used
11	Invalid operation
12	Divide by zero
13	Floating underflow
14	Floating overflow
15	BCD overflow
16	Illegal operand value
17	Single instruction trap
18	Branch trap
19	Call trap
20	Breakpoint instruction trap
21	Address trap fetch
22	Address trap read
23	Address trap write
24	Address zero access
25	Descriptor range
26	Illegal index
27	Stack overflow
28	Stack underflow
29	Programmed trap
30	Disable process switch timeout
31	Disable process switch error

If bits are going to be set in S1 by software, two mnemonics can be used. D,XST1 must be used to set the bits 17-19, 21-24, or 30-31. D,S1 must be used to set the other bits.

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3.17.3. The (trap) status register S2.¶

This is a 12 bit register.

Bit	Meaning
0	Index scaling error
1	Illegal instruction code
2	Illegal operand specifier
3	Instruction sequence error
4	Not used
5	Activate from ND-100
6	Terminate from ND-100
7	Not used
8	Instruction failure (PV, MOR, CPE, MME, MSE, PGE)
9	Data failure
10	Power fail
11	Processor fault

3.17.4. The memory and cache registers.¶

The cache length is always 4K. The width may be 32, 64, or 128 bits. This corresponds to (byte) address ranges of 0-0377777, 0-0777777, and 0-177777. If one cache module is present, the width is 32 bits. If 2, the width is 64 bits, and if 4 modules are present, the width is 128 bits.

The whole cache may be used (partitions 0-3). Two partitions may be used, 0-1, 1-2, or 2-3. Only one partition may be used, 0, 1, 2, or 3. The use of the cache is controlled by the data and instruction memory control registers. There are also status registers to display the status of the instruction and data cache.

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3.17.4.1. Data memory status registers (DSTS0, DSTS1, DSTS2)¶

DSTS0¶

Bits	Meaning
0-1	Partition number
2-3	Number of partitions (0-3 means 1-4)
4	TSB-fault
5	Memory parity error
6	Cache parity error + illegal use of cache
7	Blocked. If this bit is 1, then bits 8-15 in DSTS0 and bits 12-15 in DSTS1 will be blocked (they will not change).
8	Cache parity error, cache module 0.
9	" " " " 1.
10	" " " " 2.
11	" " " " 3.
12	Memory " " " 0.
13	" " " 1.
14	" " " 2.
15	" " " 3.

DSTS1¶

Bits	Meaning
0	Memory parity error, byte 0 (bits 7- 0).
1	" " " 1 ( " 15- 8).
2	" " " 2 ( " 23-16).
3	" " " 3 ( " 31-24).
4	Cache " " 0 ( " 7- 0).
5	" " 1 ( " 15- 8).
6	" " 2 ( " 23-16).
7	" " 3 ( " 31-24).
8-9	Cache module number (0-3).
10	Memory timeout.
11	Illegal partition setting.
12	Cache control parity error, byte 0.
13	" " " 1.
14	" " " 2.
15	Cache clear is active.

DSTS2¶

Bits	Meaning
0-7	Memory channel 0-7. If bit 10 in DSTS1 is 1, then some of the bits 0-7 will also be 1.

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3.17.4.2. Data memory control registers (DCON0, DCON1)¶

DCON0

Bits	Meaning
0-1	Select (the first) partition number
2-3	Number of partitions (0-3 means 1-4)
4	Cache disable (must be zero)

DCON1

Bits	Meaning
0-1	Select cache module no. for bits 0-7, DSTSL
2	HIC (hit in cache).
3	Clear block.
4	TSB trap enable.
5	Memory parity error trap enable.
6	Cache parity error trap enable.
7	Memory out of range trap enable.

3.17.4.3. Instruction memory status registers (ISTS0, ISTS1, ISTS2)¶

These registers have the same format as the data memory status registers.

3.17.4.4. Instruction memory control registers (ICON0, ICON1)¶

These registers have the same format as the data memory control registers.

3.17.5. Memory modus register (MMOD)¶

Bit	Meaning
0	Alternative address area (default).
1	Alternative address area selected by ALTMOD.
2	Lock until write (not used yet)
3	Data do not use cache
4	Instruction do not use cache
5	Instruction memory reference from micro code

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3.17.6. Limit Registers (HL, LL)¶

These higher and lower limit registers contain 32 bit logical addresses. They are constantly compared to logical program and data addresses, and may give a trap condition if the proper address traps are enabled.

To get an address trap, the proper bit in TE must be set to 1. In addition, if the address of a memory reference (fetch, read or write) is called ADDR, trap depends on the value of D, SETLIM:

D, SETLIM	Condition	Trap Condition
0	LL < ADDR .AND. ADDR < HL	is true gives trap
1	LL < ADDR .OR. ADDR < HL	is true gives trap

When the ND-500 has memory management, and bits 31-27 in ADDR are all zero, the segment register will be taken as the uppermost 5 bits of ADDR in the comparison with LL and HL.

3.17.7. Memory Management Substitute Registers¶

ND-500 may be without memory management. Then, there will be some additional registers:

DZPA and IZPA: Data and instruction memory zero point adjust registers. They are 14-bit registers and contain page numbers. A page has 2K bytes. These registers point to the physical page in the memory where the first page of the program itself is loaded.

DUPL and IUPL: Data and instruction memory upper page limit register. They are similar to DZPA and IZPA, and point to the program's last physical page in the memory.

DCINHLU, DCINHLL, ICINHLU, and ICINHLL: Data and instruction memory cache inhibit limit registers, lower and upper. They are similar to DZPA and IZPA, and inhibit write into the cache memory when the actual program's physical page number is in the range lower to upper (LL <= pageno <= LU).

DRADDRL, DRADDRM, IRADDRL, IRADDRM: Data and instruction memory most significant real (physical) address registers. DRADDRL and IRADDRL contain 16 bits, and DRADDRM and IRADDRM contain 8 bits. A real address is a 24-bit byte address (a real address has actually 25 bits, but the most significant bit is removed). The page number in DZPA/IZPA multiplied by 04000 is added to a program's logical data and instruction addresses, and the result goes to the real address registers. If errors occur, the real address registers are locked (that is, new real addresses will not be loaded into them before the clear-block bit in DCON1/ICON1 is set).

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3.17.8. Memory management registers.¶

There are two sets of these registers, one for the data memory and one for the instruction memory.

A real address is a logical address translated by the memory management system. The translated address is then shifted one position to the right, thereby discarding bit 0. The real address is therefore a halfword address.

3.17.8.1. Scratch files (ISCRF, DSCRF).¶

These are two sets of 16 16-bit registers. Such a register is addressed by loading ISCFA or DSCFA with a number in the range 0-15. After each access, ISCFA or DSCFA is incremented by 1, modulo 16.

3.17.8.2. Status registers (IMSTS, DMSTS).¶

Bit	Name	Meaning
0	PALIT	0: ALIT mode. Locked by TSB-fault.
1	SMM0	0: SEGEQ (same segm). Locked by TSB-fault. The segment register and bits 31-27 of the logical address are equal.
2	SMM1	0: SEGZ (zero segm). Locked by TSB fault. Bits 31-27 of the logical address are zero.
3	PUS	1: Real-addressed page is used.
4	WIP	1: Real-addressed page is written into.
5	USED	0: Used. Dynamic USED-status of the hashed part of TSB. Only valid if bit 13=0.
6	TSBF	1: TSB-fault [PON=0: 0: PON=1: 1 if bit 5=1 or not match].
7	NEWS	0: New segment (1 when DMSTS). Bits 31-27 of the logical address are not all zero, and they are not equal to bits 4-0 of the segment register.
8	MMTR	1: MM-trap (locked. Inclusive or of bits 6, compl(7), 9, 10,23).
9	ALTPV	1: ALIT protect violation.
10	WRPV	1: Write protect violation.
11	PON	1: Paging on.
12	TSBC	1: TSB clear is active (not completed). Match not found in sequential TSB, if TSB fault. Sequential TSB is accessed only if TSBF = 1 and if FAS2 = 1 (in IPROCC/DPROCC) and if USED = 0 (in actual hashed TSB entry)
13	FAS2A	Match not found in sequential TSB, if TSB fault. Sequential TSB is accessed only if TSBF = 1 and if FAS2 = 1
14	SPARE	Not defined.
15	SPARE	Not defined.
16	SP0	1: Parity error 0 (PROCC-2, DMOJ-4).
17	SP1	1: Parity error 1 (DOM5-7, SEG0-4, AD19-26).
18	SP2	1: Parity error 2 (AD11-18).

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	Register	Description
19	SP3	1: Parity error 3 (BSG0-15).
		Page number + two dummy bits.
20	SP4	1: Parity error 4 (the three permit bits). See ICSEG/DCSEG, bits 5-7.
21	SPARE	0
22	SPARE	0
23	BUFFP	1: OR-ed parity error (0 if PON=0 or not used).
24	TEO0	0: Match on PROC and DOM bit 0-4.
25	TEO1	0: Match on SSGM (or bits 27-31) and DOM bit 5-7.
26	TEO2	0: Match on log. addr. bits 11-18.
27	TEO3	0: Match on log. addr. bits 19-26.
28	USED	0: used. Static USED-status of the hashed part of TSB.
29	SPARE	Not defined.
30	SPARE	Not defined.
31	SPARE	Not defined.

Locked bits are unlocked when the memory management is turned off, or when the TSB is written into.

3.17.8.3. Logical Address (ILADDR, DLADDR)¶

These two 32-bit registers hold the instruction and data logical addresses.

3.17.8.4. WIP/PGU Broadside (IWIPGU, DWIPGU)¶

A broadside is a 16-bit extract from a 16K bit buffer. There are two such buffers, one for WIP (written in page) and one for PGU (page used). The 16 bits represent one group of 16 pages. Each group is addressed by means of the 10 most significant bits of the real address. Bit 0 represents the page with the lowest page number of the 16, bit 15 represents the page with the highest page number. To read WIP or PGU, bit 9 in IMCNTR or DMCNTR has to be set. Then bit 7 in IPROCC or DPROCC selects either WIP or PGU. If 1, WIP is selected, and if 0, PGU. Default for this bit is 0.

3.17.8.5. Real Address (IRADDR, DRADDR)¶

These two 24-bit registers hold the instruction and data real addresses. A real address is a logical address translated by the memory management system, and then divided by 2. The result is a halfword address.

3.17.8.6. Control Registers (IMCNTR, DMCNTR)¶

Bit	Meaning
4	Clear ITSB or DTSB.
9	Start to read IWIPGU or DWIPGU.

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A short list of registers, IOX instructions etc.¶

3.17.8.7. Scratch file address (ISCFA, DSCFA)¶

Two 4-bit registers, each pointing to one of the 32 scratch file registers (16 in each set).

3.17.8.8. Process control registers (IPROCC, DPROCC)¶

Bit	Name	Meaning
0	PROC0	Bit 0 of process number.
1	PROC1	Bit 1 of process number.
2	PROC2	Bit 2 of process number.
3	PON	Paging on.
4	TSBD	Disable TSB. 1: writing into TSB, 0: reading.
5		Not used.
6	FAS2	Enable use of sequential TSB (STSB).
7	SWIP	Select WIP-part of IWIPGU/DWIPGU (default 0).

3.17.8.9. Domain registers (IDOMR, DDOMR)¶

Two 8-bit registers, containing the main domain number (0-255). In the ND-500 Reference Manual, DOMR is called CED (Current Executing Domain).

3.17.8.10. Alternative domain registers (IADOM, DADOM)¶

Two 8-bit registers, containing the alternative domain number (0-255). In the ND-500 Reference Manual, ADOM is called CAD (Current Alternative Domain).

3.17.8.11. Current segment registers (ICSEG, DCSEG)¶

Two 8-bit registers, containing the current segment number in bits 0-4, and the protect status in bits 5-7.

Bit	Meaning
5	0: Shared segment status. 1: Not shared
6	0: Parameter access permitted. 1: Not permitted
7	0: Write permitted. 1: Not permitted

In the ND-500 Reference Manual, CSEG is called CES (Current Executing Segment).

3.17.8.12. Alternative segment registers (IASEG, DASEG)¶

Similar to current segment registers, but containing alternative segment number and status. In the ND-500 Reference Manual, ASEG is called CAS (Current Alternative Segment).

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3.17.8.13. Translate speed-up buffer page (ITSB, DTSB)¶

Two buffers, each contains 768 entries. Each entry contains:

3 process number bits
8 domain number bits
8 segment number bits (3 of these are protect status bits)
16 logical address bits (logical address bits 26-11)
14 page number bits (the page part of the real address)
2 dummy bits

One buffer is for data and one for instruction memory. Each buffer is divided into two sections. The lower section, with 512 entries, is addressed by a hashing algorithm, and the upper, with 256 entries, is addressed sequentially.

The hashing algorithm computes a 9-bit index by EXCLUSIVE OR-ing three numbers A, B, C. In the following, if AD31-27 are all zero, SEG4-0 comes from the segment register, bits 4-0. If AD31-27 are not all zero, SEG4-0 comes from AD31-27 (the five most significant bits of the logical address).

			A
0	0	0	DOM0	DOM1	DOM2	DOM3
	DOM4	DOM5

			B
1	SEG0	SEG1	SEG4	SEG3	SEG2	PROC2
	PROC1	PROC0

			C
AD19	AD18	AD17	AD16	AD15	AD14	AD13
AD12	AD11

3.17.8.14. Sequential TSB address register (ISTSB, DSTSB)¶

Two 8-bit registers. Top of sequential buffer. 0 means that the sequential buffer is empty, 0377 means that it is full (255 entries). ISTSB/DSTSB must be set and updated by software (micro program).

3.17.8.15. Index for hashed or sequential TSB (IHXA, DHXA)¶

The lower 8 bits of the 9-bit index may be read and checked. There is one index for instruction memory, and one for data. Either the computed index for the hashed part of TSB is read, or ISTSB/DSTSB. This depends upon the value of bit 13 (FAS2A) of the status register (TMSTS/DMSTS). If this bit is 1, ISTSB/DSTSB is read. If it is 0, the computed index for the hashed part is read.

The most significant bit of IHXA/DHXA can not be read. It is assumed to be the opposite of AD19, when FAS2A=0.

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A Short List of Registers, IOX Instructions etc.¶

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How to use the programs¶

4. How to use the programs¶

The programs may be run in three different ways: without SINTRAN (stand-alone), one by one with SINTRAN, or all programs in sequence, with SINTRAN.

4.1. Stand-alone¶

To run the programs without SINTRAN, a diskette with the programs in BPUN format (as written on the diskette by MAC with the MAC command )BPUN ) must be used. Insert the diskette in the floppy disk drive, unit 0. Press MASTER CLEAR and type 1560k on terminal 1. The floppy monitor will be read from the diskette and respond by printing an asterisk. Type LOAD COMTE, LOAD SLICE, LOAD MEMIC, etc., etc., followed by carriage return, and the selected program will start.

4.2. SINTRAN¶

4.2.1. Loading¶

Before the programs can be run under SINTRAN, they must be loaded as RT-programs by the RT-loader. A diskette with the programs in BPUN format is needed. Insert the diskette in the floppy disk drive. The loading procedure is the same for each program. In the following, NAME is used as the name of the RT-program, d=directory, u=user, and nnn is the segment number:

Command	Response
@ENT-DIR,,F-D=1,0	Response: @
@RT-LOADER	Response: heading, asterisk.
*SET-P-T,2	Response: asterisk.
*CL-SEG,nnn	Necessary to remove previous versions.
Y	Response: asterisk.
*NEW-SFG,nnn,2,DM,,,	Response: segment number message.
*READ-BIN,(d:u)NAME,,	Response: asterisk.
*SET-L-A,nnn,177777	Response: asterisk.
*DEC-P,NAME,,	Response: asterisk.
*END	Response: asterisk.
*SET-P-T,2	Response: asterisk.
*CH-RT-D,NAME,10,nnn,,0,	Response: asterisk.
*EX	Response: @
@REL-DIR d

and the loading of the program is complete.

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How to use the programs¶

4.2.2. Running one program at a time¶

To start one of the programs, log in as user SYSTEM or RT on terminal 1. Type the commands

@RT,NAME
@LOG

and the program will start on terminal 1, when it is free to use.

It is also possible to log in as user RT on any terminal and start the background program STMIC (short for STart MICro test program). Before this can be done, the file STMIC:BPM must have been loaded and dumped by the commands

@PLACE,STMIC
@DUMP,STMIC,0,0

by the user RT. STMIC will ask for which RT program to start, and then it will start this RT program directly on the terminal of the user. STMIC uses the file N500-TEST-PARAM:DATA.

4.2.3. Running all programs in sequence¶

It is possible to run all the programs in sequence, one after another. This requires the loading and starting of another RT-program called HAREM. This program is able to start any of the micro test programs. When HAREM is started, it will ask for all parameters needed, put them on a file, and start (for instance) COMTE. When COMTE has completed a run, it will give control back to HAREM, which will then start SLICE, and so on. When the last one is done, it will start the first one again. The programs will take their parameters from the file which has the name:

N500-TEST-PARAM:DATA

If the file does not exist, HAREM will create it as a continuous file with one page and save the parameters on it. This means that user RT must have some free pages.

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How to use the programs¶

4.3. Break characters¶

The program execution may be interrupted by break characters, which act as commands. When a character is typed on the terminal, the program will stop normal execution and respond with the appropriate action, perhaps after a slight delay. After the proper action for the break character is carried out, the program will continue automatically, or ask for another break character. The break characters are letters only, with one exception:
If escape is typed, the program will halt and wait for the next break character. If any character other than a break character is typed, an error message will be printed, and the program continues. Escape may also be typed as a response to questions from the programs. Another break character must then be typed. This may be useful when the user does not want to answer the question, but instead wants to restart the program, etc.
The break characters are:

Character	Description
C	Octal control store dump. Will ask for first and last address of the control store area to be dumped. Each control store location is dumped as an address and 9 16-bit numbers. After this, the program will be in one-by-one mode.
D	Display current test subroutine (symbolic). Lists the symbolic ND-500 micro code if the test is micro programmed. If not, pseudo assembly code is listed.
E	End of program.
F	Flip (switch) simulated OPR bit. Will ask for bit number of the bit to flip. After this, the specified bit in the simulated OPR will be alternately 1 or 0.
G	ND-500 register dump. A micro program will be started. It will read and send the contents of most of the ND-500 registers to ND-100 for dumping. After this, the program will be in one-by-one mode.
I	Initialise the program. The program is restarted at its very beginning.
L	LMP. The value of the user register is dumped. Useful in the case where ND-100 is without a front panel. This is a 16-bit register.
M	ND-500 memory dump. The first and last ND-500 memory address of the area to dump will be requested. A micro program will be started. It will read from the ND-500 memory and send to ND-100 for dumping. After this, the program will be in one-by-one mode.
N	Start the next test subroutine.
O	OPR. The value of simulated OPR will be printed out. The program will not continue before a new value, or CR (carriage return) is given. CR means that the old value will remain unchanged. The simulated OPR is a 32 bits register.

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How to use the programs¶

O
OPR. The value of simulated OPR will be printed out. The program will not continue before a new value, or CR (carriage return) is given. CR means that the old value will remain unchanged. The simulated OPR is a 32 bits register. Most of the routines in COMME, though, will use only the lower part of OPR.

P
Start the previous test subroutine.

R
Repeat the current test subroutine. After this, the program will be in one-by-one-mode.

S
Stop. Returns to the last question in the initiation. After this question has been answered, a memory initiation routine will set some memory registers and clear the cache. This is very useful whenever the power has been turned off.

T
Trace micro program addresses. Will trace an already loaded micro program, and print out the addresses of the micro program as it is executed. It asks for start address. A sequence of micro addresses, with no jumps, will be dumped as two numbers, the first and the last of the sequence. It is also possible to specify a break address, and to have printed the last 0100 micro addresses before the break. After this, the program will be in one-by-one mode.

U
User micro program. The user may enter his own micro program, or modify an already loaded one, and then start the program. Before the program is started, the ND–500 DATA-IN register is loaded with simulated OPR. If ND–500 unlocks, the micro address is printed, and the ND–500 DATA-OUT register is read by ND–100 and dumped in three different formats. The micro program is then continued. After this, the program will be in one-by-one mode. The user micro program is described in a separate chapter.

W
Write error messages. Used to turn on error messages in one-by-one mode.

X
Exclude error messages. Used to turn off error messages in one-by-one mode.

esc
Wait for the next break character.

4.4. The A (all) and O (one-by-one) mode¶

A program can be run in A mode or O mode. A means that the routines in the program are all run, one after another. When all the routines have been executed, the process is repeated. O means that only one routine is run, repeatedly. This continues until a break character is typed, for instance N or P. When the programs are run under HAREM control, the mode is always A. When the mode is A mode, and a routine has printed the maximum number of error messages, the next routine is entered immediately.

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How to use the programs¶

4.5. The user register¶

The user register may be displayed on the ND-100 front panel. The different subroutines use this register for the display of test values, addresses, etc. This may be helpful when the tests are run, because one is able to follow the progress of each test. The contents of the user register is described for each test.

4.6. Recommended executing sequence¶

It is important that the programs are run in a proper sequence. The first run should be COMWF, and maximum control store address should be specified as zero. The communication between ND-100 and ND-500 will then be tested only from ND-100. After this, SLICE should be run, to check that the sequencing works. When this is OK, COMWF should be run with the maximum control store address different from zero, to test the communication from the ND-500 side also. After this, SLICE should be run, and MEMMC, if ND-500 has memory, and then the remaining programs. At present, the maximum control store address is usually specified as 010000.

4.7. Stop on full page¶

It is possible to make the program halt when a full page has been written on the terminal. A full page has 22 lines. To continue, the user must type one character. The program will then continue. The character will be ignored by the program and cannot be used as input. If the user wishes to type a break character when the program has written a full page, he should first type the escape character, and then the break character.

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How to use the programs¶

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The User Micro Program¶

5. The User Micro Program¶

5.1. Description of the Commands¶

When the user types the break character U, a special program is entered. It makes it possible for the user to create, modify, and start his own micro program. This special program has its own set of commands:

Command	Description
C	Control store dump
D	Disassembly of micro instructions
G	Get back saved micro program (see P)
H	Help (list the commands)
K	Continual master clear
L	Look-at control store or memory
M	Mnemonics list
P	Put octal micro program into the save area
R	Run
S	Symbolic assembly
esc	Exit. Waits for break character

When the program is ready for a command, it prints U:. One of the command letters should then be typed by the user. If a letter is typed before the program is ready for a command, it will be taken as a break character. In this way, the OPR register may be changed while the user micro program is executed. Below follows a description of the commands:

C This is the usual control store dump.

D The contents of the control store will be disassembled into symbolic micro instructions. The first and last control store addresses will be requested. It is possible to output the disassembled micro instructions to a file, if the test program runs under SINTRAN. The file name will be requested.

G Gets back a saved octal micro program. There is a memory area in ND-100 with room for 0200 (128) micro instructions. If a micro program has been saved (Put) there, it will be loaded back into the proper addresses in the control store.

H Help. Will print a list of commands.

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The User Micro Program¶

K¶

Continual master clear (please excuse the K, as C was already used!). This routine will first call the master clear routine, and then remove the stop bit. Then, it will give continual master clear with a frequency determined by the OPR register. OPR=0 will give the highest frequency, and OPR=077777 will give the lowest. Continual master clear is very useful for debugging, as it starts the micro program in address 0 over and over again.

L¶

Look-at control store (C), instruction memory (I), or data memory (D). If the next character typed is C, this can be used to inspect and maybe change the octal contents of the control store. The routine will ask for control store address, and then print out the contents of the control store, one part at a time. After an octal number has been printed, the user can change it by typing another number, followed by CR (carriage return). If no change is wanted, CR must be typed. This proceeds until the user types a point (full stop) instead of a new number or CR. The program will then ask for the next command.

If the next character typed is I or D, the instruction or data memory may be inspected and/or changed. The routine will first initiate some memory registers and clear the cache. After this, the procedure is the same as for look-at control store.

M¶

This command will produce the list of the micro code mnemonics, together with their values. There are over 720 such mnemonics.

P¶

Puts an octal micro program into the save area, which is an area in the ND-100 memory with room for 128 micro instructions. The routine will request the first and last control store addresses. It is very useful to save an octal micro program while the ND-500 is being debugged. If the user wants to put a printed circuits board on an extension board, for instance, the power must be turned off, and his micro program will disappear. Therefore, it should first be saved by typing P.

R¶

Run a micro program. The start address will be requested. Before the micro program is started, the OPR register is loaded into IODIN (the DATA-IN register), and then the micro program runs until it is stopped by the user, or until ND-500 unlocks. When ND-500 unlocks, ND-100 will print out the micro address of the next instruction and the value of IODOUT (the DATA-OUT register) in three different formats, word, halfword, and byte. After this, ND-100 will load the value of OPR into IODIN and continue the micro program. The user can stop all this by typing the break character u. Control will then be returned to the user program. Remember that the OPR register may be changed at any time during the run of a micro program, but IODIN will not be loaded with this value unless ND-500 unlocks.

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The User Micro Program¶

Symbolic Assembly¶

The control store address will be requested. The user types mnemonic codes, separated by space, and the program will translate them to octal. When a semicolon is typed, the octal micro instruction will be loaded into the control store. Long arguments and jump addresses must be typed as two 16 bit octal numbers. For instance, a long argument may be typed as 6,6. The jump address 5 must be typed as 5,0. A short argument, for instance 3, can be typed as 0,3 or only as 3. After the last semicolon, a point (full stop) will end the assembly. An incorrect mnemonic will be ignored, or it may be erased (before the separating space is typed) by typing ctrl W. If the same mnemonic is typed twice, the whole micro instruction is deleted (set to zero).

It is possible to assemble symbolic files from the disk, if the test program runs under SINTRAN. The file name will be requested. In this case, comments (%) are skipped during the assembly. If the file is not ended by a full stop (.), end-of-file will simulate it.

5.2. Some Useful Micro Instructions¶

ALU,ADIR A,XD,IODIN SLOW1 D,IODOUT NEXT;
    % This loop can be used to
    % check the bus from IODIN
    % through ALU to IODOUT by
UNLOCK NEXT; % changing simulated OPR.
W,XD NEXT;
JMP BACKTHREE;

ALU,ADIR A,XD,SARG SLOW1 2 D,TAG NEXT;
    % read STATUS to IODIN-1
W,IO NEXT;

ALU,ADIR A,XD,SARG SLOW1 3 D,TAG NEXT;
    % write IODOUT-1 to STATUS
W,IO NEXT;

In the next example, the MOST bit (0200) selects IODIN-2.
The two parts of MAR will be read alternately, and are not dependent on the MOST bit.

ALU,ADIR A,XD,SARG SLOW1 0 D,TAG NEXT;
    % least sign MAR to IODIN-1
W,IO NEXT;
ALU,ADIR A,XD,SARG SLOW1 0200 D,TAG NEXT;
    % most sign. MAR TO IODIN-2
W,IO NEXT;
ALU,ADIR A,XD,IODIN SLOW1 D,IOODUT NEXT;
ALU,ADIR A,XD,SARG SLOW1 0201 D,TAG NEXT;
    % IODOUT-2 to MAR
W,IO NEXT;
ALU,ADIR A,XD,SARG SLOW1 1 D,TAG NEXT;
    % IODOUT-1 to MAR
W,IO NEXT;

ALU,ADIR A,XD,SARG SLOW1 6 D,TAG NEXT;
    % read 16 bit from ND-100
W,IO NEXT;
    % MAR was already set
ALU,ADIR A,XD,IODIN SLOW1 D,IODOUT NEXT;
    % 16-bit word to IODOUT
ALU,ADIR A,XD,SARG SLOW1 7 D,TAG NEXT;
    % write to next ND-100 word
W,IO NEXT;
    % MAR was autom. incr.

In the examples above, with tag codes 0 to 7, it is the least significant part of IODOUT that is used. If the most significant part is wanted, 0200 must be added (0200 to 0207).

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The User Micro Program¶

ALU,A=B A,X#0 B,X#0 SEM COND,MZRO NEXT;  % condition is now true
C,SEQ JMP PREVIOUS F,NEXT;
UNLOCK NEXT;
W,ND NEXT;                                % stop
JMP BEGIN;                                % continue here after stop

ALU,ADIR A,XD,SARG SLOW1 0100 D,LC NEXT;  % loop counter:=0100
LCDECR NEXT;                              % decrement loop counter
ALU,ADIR A,XD,LC SLOW1 D,IOODUT NEXT;
UNLOCK NEXT;
W,ND NEXT;
JMP BACKFOUR;                             % jump to new decrement

In the following example, the contents of X#0 is written to the memory. X#1 holds the memory address.

ALU,ADIR A,XD,SARG SLOW1 0 D,MMOD NEXT;  % data memory
ALU,ADIR A,X#0 PASSAB AB,IX IX1 MEM,WR4 W,MEM NEXT;

ALU,ADIR A,XD,SARG SLOW1 040 D,MMOD NEXT;  % instr mem.
PASSAB AB,IX IX1 AD,ILC NEXT;
ALU,ADIRC A,X#0 SLOW1 D,IDAT MEM,WR4 W,MEM PASSAB NEXT;

Next, the contents of the memory word whose address is in X#1, is read to X#0.

ALU,ADIR A,XD,SARG SLOW1 0 D,MMOD NEXT;  % data memory
PASSAB AB,IX IX1 MEM,RD4 W,MEM NEXT;
ALU,ADIR A,DATA D,X#0 NEXT;

ALU,ADIR A,XD,SARG SLOW1 040 D,MMOD NEXT;  % instr mem.
PASSAB AB,IX IX1 AD,ILC NEXT;
A,XD,IDAT XMOV D,CONST MEM,RD4 W,MEM PASSAB NEXT;
ALU,ADIRC A,XD,CONST SLOW2 D,X#0 NEXT;

Next, the B-operand is converted from byte to halfword:

ALU,BDIR B,X#0 TYP,BY BYTH SLOW1 D,IOODUT NEXT;

Please remember that a lot of small micro programs may be studied by typing D when the test programs are running!

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COMTE - the ND-100/ND-500 communication test program¶

6. COMTE - the ND-100/ND-500 communication test program¶

6.1. General Information¶

COMTE tests the communication between ND-100 and ND-500. The first 22 routines are not verification routines. The first 39 routines are not micro programmed. They just use IOX instructions from the ND-100, the ND-500 being passive. If the user wants to know what the different routines do, the break character D will dump the symbolic micro code of the test, or pseudo assembly code. The break character C may then be used to inspect the octal micro program. It is always loaded from the minimal control store address.

6.2. How to load and start the program¶

Stand-alone: MASTER CLEAR. 1560&. *LOAD COMTE.

SINTRAN: @RT COMTE and possibly @LOG, or @STIMIC.

COMTE first asks whether the user wants to run on another terminal. If the answer is Y, COMTE will request a decimal logical device number (SINTRAN), or an octal physical device number (stand-alone).

If the program runs under SINTRAN, it will reserve the ND-500 and possibly some memory (COMTE needs no ND-500 memory). COMTE will ask all the necessary questions.

COMTE asks for maximum control store address. Answer 0, and the micro programmed routines will not be used. Answer 02000, 010000, etc., depending on the hardware configuration, and tests both with ND-500 passive and ND-500 active (micro programmed) will be run.

COMTE asks for minimum control store address. The answer should be less than maximum control store address. If this address is different from zero, the micro programs will be relocated when they are loaded.

COMTE asks for stop on full page. If you want the program to pause when 22 lines have been printed on the terminal, you should type Y, otherwise N. Stop on full page is useful when you are using a screen terminal.

COMTE asks for TEST, VERIFY, OR BOTH?

Answer	Routine Execution
T	Only routines 1 to 22 are run.
V	Only routines 23 to 49 are run.
B	All routines are run.

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COMTE - the ND-100/ND-500 communication test program¶

COMTE asks if you want information. If the answer is Y, a list, describing the two modes and the break characters, is printed.

COMTE asks if the tests are to be run all in succession, or one by one. If the answer is the letter O, COMTE will ask for the routine number, and if error messages are wanted. Then the routine with the given number will be run repeatedly.
If the answer is A, all routines will be run in succession in a ring.

The execution of the program may be interrupted and changed at any time by the typing of break characters.

6.3. The test routines¶

6.3.1. TST01 Continual master clear¶

Will give master clear (IOX MCLR) continually. The frequency depends on simulated OPR. This routine may be used to start a micro program in address 0 again and again, if the stop bit is off.
The user register is not used.

6.3.2. TST02 Set and reset stop bit¶

Will switch (flip-flop) the stop bit (IOX RETG) continually (from bit 1 in the A-register).
The user register is not used.

6.3.3. TST03 Set and reset activate¶

Will switch (flip-flop) the activate bit (IOX LCON) continually (from bit 2 in the A-register).
The user register is not used.

6.3.4. TST04 Set and reset reverse tag bus bit¶

Will switch (flip-flop) the reverse tag bus bit (IOX RETG) continually (from bit 0 in the A-register).
The user register is not used.

6.3.5. TST05 Test 3022 control register (bits 3-2 always 10)¶

Will load the control register with the contents of simulated OPR, and then read it back and display it in the user register. Bit 3 is always set to 1, and bit 2 is always set to 0.

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COMTE - the ND-100/ND-500 communication test program.¶

6.3.6. TST06 Test 3022 status register.¶

Will load the status register with the contents of simulated OPR, and then read it back and display it in the user register.

6.3.7. TST07 Test 3022 memory address register.¶

Will load MAR with the contents of simulated OPR (the lower 24 bits of the 32 available), and then read it back and display it in the user register. If the lowermost 16 bits of the read back value are all zero, the uppermost 8 bits will be displayed. If not, the lowermost 16 bits are displayed.

6.3.8. TST08 Test 3022 data register.¶

Will load the data register with the contents of simulated OPR, and then read it back and display it in the user register.

6.3.9. TST09 Test 3022 lower limit register.¶

Will load the lower (DMA) limit register with the contents of simulated OPR, and then read it back and display it in the user register.

6.3.10. TST10 Test 3022 upper limit register.¶

Will load the upper (DMA) limit register with the contents of simulated OPR, and then read it back and display it in the user register.

6.3.11. TST11 Test tag dataway.¶

Simulated OPR is used as tag code (write-tag). The tag code is read back (IOX RTAG) and displayed in the user register.

6.3.12. TST12 Test DATA-IN to DATA-OUT.¶

Data is taken from simulated OPR, written to 5015 via the DATA-IN register, and then read from the DATA-OUT register. Only the least significant part is tested. The result is displayed in the user register.

6.3.13. TST13 Test DATA-IN to WA-reg to DATA-OUT.¶

Data is taken from simulated OPR, written to 5015 via the DATA-IN register and the WA (write-address) register is clocked. Then the WA register is enabled, and data is read from the DATA-OUT register. The result is displayed in the user register.

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COMTE - the ND-100/ND-500 communication test program¶

6.3.14. TST14 Test DATA-IN to BREAK-reg to DATA-OUT¶

Data is taken from simulated OPR, written to 5015 via the DATA-IN register, and the BREAK register is clocked. Then the BREAK register is enabled, and data is read from the DATA-OUT register. The result is displayed in the user register.

6.3.15. TST15 Test DATA-IN to CSCNT-reg to DATA-OUT¶

Data is taken from simulated OPR, written to 5015 via the DATA-IN register, and the CSCNT register is clocked. Then the CSCNT register is enabled, and data is read from the DATA-OUT register. The result is displayed in the user register.

6.3.16. TST16 Test TAG-OUT on 5015¶

Data is taken from simulated OPR, written to 5015 via the DATA-IN register, and the TAG-OUT register is clocked. Then bit 9 (TSTTGG, 01000) is written to 5015 via the DATA-IN register, and the CSCNT register is clocked. IOX RMTG (return tag) with the A-register equal to 3, and IOX RTAG (read tag) are executed. The result is displayed in the user register.

6.3.17. TST17 Test DATA-IN to DATA-OUT, most significant 16 bits¶

Data is taken from simulated OPR and written to 5015 via the most significant part of the DATA-IN register. Then the MOST bit (0200) is written to 5015 via the least significant part of the DATA-IN register, and the TAG-OUT register is clocked. Data is read back from the DATA-OUT register without using the DJEN bit. The result, the most significant part of the DATA-OUT register, is displayed in the user register.

6.3.18. TST18 Test control signals for load control store¶

The BREAK register is filled with a 16 bit micro code word (at present, it is 0). Then simulated OPR is put into the CSCNT register. The user register is not used by this test.

6.3.19. TST19 Test control signals for read control store¶

Simulated OPR is put into the CSCNT register. Then the DATA-OUT register is read and displayed in the user register.

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COMTE - the ND-100/ND-500 communication test program¶

6.3.20. TST20 Test write-and-read one 16-bit word in the control store¶

The user has to specify a control store address and a part number in the range 0-8. After that, 9 16-bit words, all zero, are written into the specified location in the control store, and the specified address is put into the WA register. Then a loop is started, writing simulated OPR into the control store location with the specified part number in the specified address, reading it back, and displaying it in the user register.

6.3.21. TST21 Test control signals for start (from stop mode)¶

The stop bit is set, simulated OPR is put into the CSCNT register, and the stop bit is reset. The user register is not used by this test.

6.3.22. TST22 Test break (by setting WA=BREAK)¶

The stop bit is set, simulated OPR is put into the WA register and the BREAK register, and the break enable bit (0100) is put into the CSCNT register. The user register is not used by this test.

6.4. The verification routines¶

6.4.1. TST23 Verify 3022 DATA register¶

The DATA register is loaded and read by the sequence SAA 010; IOX LCON; LDA DATA; IOX TERM; SAA 0; IOX MCLR. The result is checked, and error messages are printed where applicable. The user register displays the read-back value. It will be continually incremented.

6.4.2. TST24 Verify 24 bits memory address register¶

The MAR register is loaded twice by IOX LMAR and read twice by IOX RMAR. The most significant part is loaded first, and the first part that is read back, is assumed to be the least significant part. The result is checked, and error messages are printed where applicable. The user register displays the least significant part of the read-back value. It will be continually incremented.

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COMTE - the ND-100/ND-500 communication test program.¶

6.4.3. TST25 Verify 3022 CONTROL register (Bit 2=0, Bit 4=1 clears bit 6).¶

The CONTROL register is loaded and read by IOX instructions. The result is checked, and error messages are printed where applicable. Bit 2 (the activate bit) is always 0 in this test. The user register displays the read-back value. It will be continually incremented.

6.4.4. TST26 Verify STATUS register (not bits 0, 5, 011 and 017).¶

The STATUS register is loaded and read by IOX instructions. The result is checked, and error messages are printed where applicable. Some of the bits are not part of the test, as they cannot be set or reset by IOX LSTA. The user register displays the read-back value. It will be continually incremented.

6.4.5. TST27 Verify 3022 (DMA) lower limit register.¶

The LL register is loaded and read by IOX instructions. The result is checked, and error messages are printed where applicable. The user register displays the read-back value. It will be continually incremented.

6.4.6. TST28 Verify 3022 (DMA) upper limit register.¶

The UL register is loaded and read by IOX instructions. The result is checked, and error messages are printed where applicable. The user register displays the read-back value. It will be continually incremented.

6.4.7. TST29 Verify tag dataway.¶

This routine will write tag, read it back, and check the result. Error messages will be printed where applicable. The user register will display the value that was read back (it will be continually incremented).

6.4.8. TST30 Verify dataway, least significant 16 bits.¶

The least significant 16 bits of the data path from ND-100 to DATA-IN to DATA-OUT to ND-100 will be verified. Error messages will be printed where applicable. The user register will display the value that was read back. It will be continually incremented.

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COMTF - the ND-100/ND-500 communication test program¶

6.4.9. TST31 Verify WA register¶

Data is sent from ND-100 to DATA-IN to WA to DATA-OUT to ND-100, and then checked for correctness. Error messages are printed where applicable.
The user register will display the read-back value. It will be continually incremented.

6.4.10. TST32 Verify BREAK register¶

Data is sent from ND-100 to DATA-IN to the BREAK register to DATA-OUT to ND-100, and then checked for correctness. Error messages are printed where applicable.
The user register will display the read-back value. It will be continually incremented.

6.4.11. TST33 Verify CSCNT register¶

Data is sent from ND-100 to DATA-IN to the CSCNT register to DATA-OUT to ND-100, and then checked for correctness. Error messages are printed where applicable.
The user register will display the read-back value. It will be continually incremented up to 02000.

6.4.12. TST34 Verify TAG-OUT¶

Data is sent from ND-100 to TAG-OUT. Then bit 9 (TSTTIGU, 01000) is put into the CSCNT register, and TAG-OUT is read back and checked. Error messages are printed where applicable.
The user register will display the read-back value. It will be continually incremented.

6.4.13. TST35 Verify data least significant 16 bits controlled by MOST bit¶

Zero is put into the TAG-OUT register, to ensure that the MOST bit is off. After this, data is sent from ND-100 to DATA-IN to DATA-OUT to ND-100, without using the DUEN bit. The result is checked, and error messages printed where applicable.
The user register displays the read-back value. It will be continually incremented.

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COMTE - the ND-100/ND-500 communication test program¶

6.4.14. TST36 Verify data most significant 16 bits controlled by MOST bit¶

The MOST bit (0200) is put into TAG-OUT. Then data from ND-100 is written into the most significant part of the DATA-IN register. The DATA-OUT register is read back to ND-100 without using the DUE bit, and the result is checked. Error messages are printed where applicable.
The user register will display the read-back value. It will be continually incremented.

6.4.15. TST37 Verify control store¶

This routine will check the specified part of the control store. First, it will do an address-in address test. Then it will write a test pattern once and read it 4 times, and check for errors. Error messages are printed where applicable. There are 4 different patterns. Every time the pattern is written into a control store location (144 bits), it is rotate shifted 1 left. This means that within one 144-location block, no two locations are alike. Every time a 144-bit word is read from the control store, the CSPTY bit in the 5015 CSCNT register is checked.
The user register will display the control store address, both for write and read. For write, bit 15 (017) will be set to 1.

6.4.16. TST38 Verify load of WA, BREAK, CONTROL, TAG-OUT, and read back a lot of times¶

The TAG-OUT, WA, BREAK and CONTROL registers on 5015, are loaded with 017, 036000, 140300, and 01460, respectively, and then they are read back many times. The results are checked, and error messages are printed where applicable.
The user register displays a counter.

6.4.17. TST39 Verify DATA-IN to DATA-OUT, 32 bits¶

The value of a counter is sent from ND-100 to the least significant part of DATA-IN. The complement of this counter is sent to the most significant part of DATA-IN. The least significant part of DATA-OUT is read, and then the most significant part. The results are checked, and error messages are printed where applicable.
The user register displays the least significant part of the counter.

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COMTE - the ND-100/ND-500 communication test program.¶

6.5. The micro programmed routines.¶

6.5.1. TST40 Verify write-STATUS on 3022 from ND-500 (not bits 017, 011-7, 5, 0).¶

This routine loads a small micro program into the control store and starts it. The micro program loads the STATUS register on 3022, and then unlocks ND-500. ND-100 then reads the STATUS register and checks it. Error messages are printed where applicable. If ND-500 does not unlock, a timeout message is printed.
The user register displays the STATUS register, as it is read back by ND-100. It will rotate shift left a single 1, or a single 0. Some of the bits in the STATUS register are not part of the test, as they are not controlled by a simple STATUS load from ND-500.

6.5.2. TST41 Verify write MAR on 3022 from ND-500.¶

A small micro program is loaded and started. It will load the memory address register from ND-500 and then unlock. ND-100 reads and checks the register, and prints error messages where applicable.
The user register displays the least significant part of the memory address register as it is read by ND-100. It will rotate shift left a single 1, or a single 0.

6.5.3. TST42 Verify store-in-memory (write-DATA) from ND-500.¶

ND-100 loads the memory address register. When the program is run under SINTRAN, it is loaded with 0; 017. When it is run stand-alone, it is loaded with 0; addr, where addr is an address somewhere in the program area. Then a micro program is loaded and started. This will do a DMA transfer (write) of one word, and then unlock. ND-100 will fetch the result from the DATA register and check it. If OK, ND-100 will read the memory address register and check that it has been incremented by 1. If OK, ND-100 will fetch the result from the memory and check it. Where applicable, error messages will be printed.
The user register will display the DATA register as it is read by ND-100. It will rotate shift left a single 1 or a single 0.

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COMTE - the ND-100/ND-500 communication test program¶

6.5.4. TST43 Verify read-and-write-STATUS on 3022 from ND-500 (not bits 017, 011-7, 5, 0).¶

A micro program is loaded and started. ND-500 will read the STATUS register, complement it, write it back, and then unlock. ND-100 will check that the STATUS register has been complemented, and print error messages where applicable.
The user register will display the value of the STATUS register as it is read by ND-100. It will rotate shift a single 1 or a single 0.

6.5.5. TST44 Verify read-and-write-MAR on 3022 from ND-500.¶

A micro program is loaded and started. ND-500 will read the memory address register, complement it, write it back, and unlock. ND-100 will check that the register has been complemented. Where applicable, error messages are printed.
The user register will display the least significant part of the memory address register as it is read by ND-500. It will rotate shift left a single 1 or a single 0.

6.5.6. TST45 Verify read-CONTROL-and-write-MAR on 3022 from ND-500 (not bits 6-3, always bit 2).¶

A micro program is loaded and started. ND-500 will read the control word from 3022 and write it back to the least significant part of MAR, and unlock. ND-100 will check the result. Error messages are printed where applicable.
The user register will display the value of the least significant part of MAR as it is read from ND-100. It will rotate shift a single 1 or a single 0. Bits 3-5 have to be 0 for this test, and bit 2 has to be 1.

6.5.7. TST46 Verify read-and-write-DATA on 3022 from ND-500.¶

ND-100 first loads the memory address register. Then a micro program is loaded and started. ND-500 will read a 16-bit word from the ND-100 memory (via the DATAX register), decrement the memory address register by 1, complement the 16-bit word and write it back (via the DATA register), and then unlock. ND-100 will check that the memory address register is incremented by 1, and that the data word is complemented.
The user register will display the data word as it is read by ND-100. It will rotate shift a single 1 or a single 0.

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COMTE - the ND-100/ND-500 communication test program¶

6.5.8. TST47 Verify DATA-IN to DATA-OUT, 32 bits, and then DATA-OUT-2 to DATA-OUT-1.¶

The most significant part of DATA-IN is loaded with the value of a counter. A micro program is loaded and started. ND-500 will copy DATA-IN to DATA-OUT, move the most significant part of DATA-OUT to the least significant part (thereby destroying the most significant part), and then unlock. ND-100 will check the results and print error messages where applicable. The user register displays the counter as it is loaded into DATA-IN.

6.5.9. TST48 Verify lower and upper (DMA) limit registers during DMA transfer.¶

The LL register is loaded with 0 and the UL register is loaded with 177777. After this, the MAR register is loaded with all values from 0,0 to 0377,177000 with an increment of 0400. The program checks that the status register, bit 6, is always 0 (legal DMA). Then the limit registers are loaded with 177777 and 0 (no DMA is legal). The MAR register is loaded with all values from 0,0 to 0377,177400. The program checks that the status register, bit 6, is always 1 (illegal DMA). After this, the LL and UL registers are loaded with 0 and 1. This means that DMA transfers into the memory area from 0 to 0377 are legal. A micro program is then started. It will do three DMA transfers (read) from address 0376, 0377, and 0400. Before each DMA transfer, the micro program will read S2 (ND-500 status register 2). ND-100 will check that the two first have bit 6=0 (legal), and that the last has bit 6=1 (illegal). The user register will display the uppermost 16 bits of the MAR register as it is loaded.

6.5.10. TST49 Micro programmed moving control store test.¶

This is a fairly big micro program. It consists of a little less than 400 micro instructions. When it is loaded and started, it will write into and read from the control store three different patterns. They are address+partnumber in address, complement of address+partnumber in address, and a fixed pattern with a mixture of ones and zeros. When the control store has been written and read with all three patterns, ND-500 unlocks, and ND-100 loads the micro program from the next higher control store address and starts it again. If ND-500 detects errors, it will unlock, and ND-100 will print error messages. The user register will display the load address of the micro program.

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COMTE¶

The ND-100/ND-500 communication test program.

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SLICE - the ND-500 slice test program.¶

7. SLICE - the ND-500 slice test program.¶

7.1. General information.¶

SLICE tests the ND-500 slice and sequencing: single step, sequencing through single stepping, bit mask, AIU functions, registers, etc. Only the first routine is a test routine, and the rest are verification routines. All routines test with the help of micro programs. All micro programs are loaded from the minimum control store address specified by the user in the initiation of the program. They are relocatable. After SLICE has been started, its execution may be modified and altered by typing break characters (one-letter commands).

7.2. How to load and start the program.¶

Stand-alone: MASTER CLEAR. 156O6:. *LOAD SLICE.

SINTRAN: @RT SLICE and possibly @LOG, or @STMIC.

SLICE asks for some parameters. These questions are similar to the questions asked by COMTE, with one exception. Maximum control store address should not be specified as zero. See the chapter on COMTE.

7.3. The test routines.¶

7.3.1. TST01 Test single step.¶

This is not a verification routine. It tests single step by putting the first control store address into the WA and BREAK registers. Then it puts the break enable and start address enable bits (6-7, 0300) into the CSCNT register. It activates ND-500 and removes the stop bit. After that, the program unlocks ND-500, sets the stop bit, resets the break and start address enable bits, and resets break. The user register is not used by this routine.

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7.4. The verification routines.¶

7.4.1. TST02 Verify sequencing (single step a lot of NEXT).¶

This routine starts by filling the specified part of the control store with the micro instruction NEXT. Then the micro program is started in the first control store address, and the micro program is single stepped through every micro instruction. This is done 8 times. ND-100 reads the CSA bus (control store address bus) and checks that the address has been incremented by 1 for each single step. Error messages are printed where applicable. The user register will display the control store address. When the micro program is loaded, the user register will count with an increment of 0100. When the micro program is executed, it will count with an increment of 1.

7.4.2. TST03 Verify sequencing (single step a lot of JMP *-1).¶

The control store is filled with the micro instruction JMP *-1; (jump to the previous location). In the first location, a jump to the last micro instruction in the program is inserted. When this is done, the micro program is started in its first address. ND-100 single steps through the entire micro program 8 times. It reads the CSA bus (control store address bus) and checks that it has been decremented by 1. Error messages are printed where applicable. The user register counts with an increment of 0100 when the micro program is loaded, else it counts with an increment of -1.

7.4.3. TST04 Verify sequencing (single step a lot of JSR SUB).¶

The control store is filled with the micro instruction JSR SUBR1, except for the first 4 and the last 3 locations. In the first 4 locations are loaded two subroutines jumping to other subroutines. In the last 3 are loaded two subroutines. The first one jumps to the next, and the second only returns. In this way, ND-100 will, when it is single stepping through the micro program, check the 4 level subroutine jump facility. ND-100 checks this by reading the CSA bus (control store address bus) for every single step. Error messages are printed where applicable. The user register counts with an increment of 0100 when the micro program is loaded. When the micro program is executed (4 times), it is a little more complicated. It is started in location n+4, if the first control store address is n, and the sequence of addresses will be

n	n+2	last	last-1	n+3	n+1	n+5
n	n+2	last	last-1	n+3	n+1	n+6
n	n+2	last	last-1	n+3	n+1	n+7

and so on.

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SLICE - the ND-500 slice test program¶

7.4.4. TST05 Verify sequencing (single step a lot of ALUJ, ADIR and JMPCAR and W,XD)¶

This routine verifies the computed address register. It fills the control store with the three micro instructions ALUJ, ADIR, JMPCAR; W,XD; over and over again, from address n+1 (if the first control store address is n). The ALUJ, ADIR instruction loads the computed address register with an address (different for each ALUJ, ADIR: n+4, n+7, n+012, n+015, and so on). The program is started in location n+1 (if the first control store address is n), and the CSA bus should go like this: n+1 n+2 n+4 n+5 n+7 n+010 ... ND-100 reads the CSA bus (control store address bus) and checks it. Error messages are printed where applicable.

The user register counts with an increment of 077 when the micro program is loaded. When the micro program is executed, the user register displays the CSA bus (n+1 n+2 n+4 n+5 n+7 n+010 n+012 etc.).

7.4.5. TST06 Verify sequencing (single step a lot of ALUJ, ADIR and JMPREL and NEXT)¶

This routine verifies jumps relative to the micro address. The displacement is in the computed address register. The control store is loaded over and over again with the micro instructions ALUJ, ADIR; JMPREL; NEXT; The ALUJ, ADIR instruction loads the computed address register with a displacement of -5. The program is started in one of the last ALUJ, ADIR instructions. SLICE will step through the micro program, read the CSA bus, and check it. Error messages are printed where applicable.

The user register will count with an increment of 077 when the micro program is loaded. When it is executed, it will go like this: 011 012 013 6 7 010 3 4 5 ...

7.4.6. TST07 Verify bit mask bits as A-opr and B-opr¶

This routine verifies the bit mask by letting a micro program load the #%0-%#3 registers with 4 different bit masks, and then report back to ND-100 (by doing DMA transfers). ND-100 checks that the bits are correct, loads another piece of micro program with other bit masks, and starts ND-500 once more. Error messages are printed where applicable. The bit mask is generated both as A-operand and B-operand.

The user register will count to 0100, because the routine is run 64 times (each run testing 32 A-operands and 32 B-operands).

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SLICE - the ND-500 slice test program¶

7.4.7. TST08 Verify A,BMR and B,BMR (bit mask register).¶

The 5-bit Bit Mask Register is verified by letting a micro program load it with a bit number, and then load two of the X40-Xf3 register with numbers containing only one 1-bit, decoded from the BMR. This is done with the BMR both as A-operand and B-operand. ND-500 then reports back to ND-100 (by DMA transfers), and ND-100 checks the results. Error messages are printed where applicable. ND-100 then modifies the micro program with other bit numbers, and starts ND-500 once more.

The user register displays the number of runs by counting to 040, since the BMR register can hold 32 different values (it has 5 bits).

7.4.8. TST09 Verify all logical AIJ functions.¶

All the 16 logical AIJ functions are verified. Those with only one operand are checked first. All four data types, word, float, halfword, and byte, are used. There are 66 operands: 0, -1, single 1-bit (32 different operands), single 0-bit (32 different operands). A micro program is loaded that executes the logical function and reports back to ND-100 by doing DMA transfers. ND-100 checks the results and prints error messages where applicable. Then another micro program is loaded, and the process is repeated. If the program is run in one-by-one mode, all functions, or only one, can be tested. When only one function is selected, the routine will run this function until N or P is typed, thus making it possible to extensively check a specific function.

The user register displays the octal value of the logical function in bits 2-6, with bit 6 always equal to 1, and the data type in bits 0-1.

7.4.9. TST10 Verify all arithmetical AIJ functions.¶

The 16 arithmetical AIJ functions are verified in numerical order. Those with no or only one operand will execute faster (0, 3, 014, 017). The four data types word, float, halfword, and byte, are all used. The four carry types forced zero, forced one, carry from status, and carry from micro status, are all used. There are 66 operands: 0, -1, single 1-bit (32 different operands), single 0-bit (32 different operands). ND-100 loads a micro program and starts it. ND-500 then executes an arithmetical AIJ function, with a given data type, carry type, and zero, one, or two operands. The result is sent back to ND-100 by DMA transfers, and ND-500 unlocks. ND-100 then checks the results and prints error messages where applicable. The micro program is modified, loaded and started, and the whole process is repeated. If the program is run in one-by-one mode, all functions, or only one, can be tested. When only one function is selected, the routine will run this function until N or P is typed, thus making it possible to do an extensive check of a specific function.

The user register displays octal arithmetical AIJ function code in bits 4-8 (bit 8 is zero), data type in bits 2-3, and carry type in bits 0-1.

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SLICE - the ND-500 slice test program.¶

7.4.10. TST11 Verify ND-500 registers (X#0-X#3, AM#0-AL#0-AM#1-AL#1, etc.).¶

The ND-500 registers are tested, 4 32-bits registers at a time, by loading patterns into them. A micro program loads the registers, sends their contents to ND-100 by DMA transfers, and unlocks. ND-100 checks the results and prints error messages where applicable. Then the micro program is modified by inserting the next shifted version of the pattern, and the program is reloaded and restarted. When the pattern has been completely used, new register codes are inserted into the micro program, and the process is repeated. Four 128-bit patterns are used, and each of them is rotate shifted left for each run. If the program is run in one-by-one mode, all registers, or only one register block, can be tested. When only one register block is selected, the routine will check this specific register block over and over again, until N or P is typed.

The user register displays the number of the register block under test, in bits 9-13, pattern number in bits 7-8, and shifted version number in bits 0-6. There are 024 register blocks.

7.4.11. TST12 Verify scratch registers as A-block and B-block.¶

This routine is run 4 times, by a micro program loaded and started by ND-100. All the scratch registers are loaded with patterns, the first two times by ADIR instructions, the next two by ADRIC instructions. In the first and third run, the scratch registers are copied to X#0-X#3 by A-operands, and in the second and fourth run, by B-operands. The X#0-X#3 registers are sent to ND-100 by DMA transfers, and ND-100 checks the results. Error messages are printed where applicable.

The user register displays the run number (0 to 3).

7.4.12. TST13 Verify sequencing (conditional jumps).¶

This routine checks conditional jumps. It loads a micro program and single steps through it. For every single step, the CSA bus, containing the control store address, is read and compared to an expected value. In case that the address is not at all like the expected value, an error message containing the two numbers will be printed. Otherwise, the error messages will contain information about status or micro status, the condition that failed, etcetera. The user register will contain the control store address, and bits 10-15 will be continually incremented.

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SLICF - the ND-500 slice test program¶

7.4.13. TST14 Verify loop counter decrement (JCDECR)¶

The control store is filled with the micro instruction JCDECR; IODIN is loaded with a start value. The micro program is started. The start value is copied to the loop counter, and all the micro instructions are executed, thereby decrementing the loop counter. The result is copied to IODIOUT, and ND-500 unlocks. ND-100 reads and checks this value, and prints error messages where applicable. Then another start value is loaded into IODIN, and the process is repeated.

The user register will first display control store load address, and then the different start values that are loaded into IODIN.

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MEMIC - the ND-500 cache and memory test program.¶

8. MEMIC - the ND-500 cache and memory test program.¶

8.1. General information.¶

MEMIC tests the ND-500 memory and cache. There are two channels, one for data, and one for instructions. The same memory may be used both as instruction and data memory. The first two routines are not verification routines. All the routines are micro programmed. They are loaded and started by ND-100. When the program has been started, its execution may be modified and altered by typing break characters (one-letter commands).

8.2. How to load and start the program.¶

Stand-alone: MASTER CLEAR. 1560&. *LOAD MEMIC.

SINTRAN: @RT MEMIC and possibly @LOG, or @STMIC.

MEMIC first asks whether the user wants to run on another terminal. If the answer is Y, MEMIC will request a decimal logical device number (SINTRAN), or an octal physical device number (stand-alone).

If the program runs under SINTRAN, it will reserve the ND-500 and possibly some memory, if the user wants it. MEMIC will ask all the necessary questions.

Which memory addresses to use when MEMIC is run, depends on the circumstances. MEMIC may be run under SINTRAN, or stand-alone. It may check only memory, only cache, or both cache and memory. It may run with memory management on, or off, or without memory management at all. It can run in a system where the ND-100 and the ND-500 both have their own memory, or where the ND-100 at least has memory which the ND-500 cannot reach. It can also run in a system where the ND-100 and the ND-500 share all the memory (user, beware!). The memory configuration of a system may be checked by the stand-alone test program MPEST. It will print out two memory maps, one for the ND-100 and one for the ND-500. If there is shared memory, the ND-100 value of address 0 of the ND-500 address space will also be printed out. Below follows some advice on how to use MEMIC (memory management is shortened to MM):

Stand-alone and no MM.
If the ND-100 has local memory: specify any addresses.
If the ND-100 and the ND-500 share the memory: specify addresses from 0400000 and up. This is the start address of (ND-100) bank 1, and the micro programs started by ND-500 will not overwrite MEMIC itself.

Stand-alone and MM off.
The same as for no MM above.

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MEMIC - the ND-500 cache and memory test program¶

Stand-alone and MM on¶

If the ND-100 has local memory: specify any addresses. Be aware that an initiation micro program fills the TSB (translation speed-up buffer). If too much memory is specified, the memory addresses specified by the user will be changed by the program, because the TSB is filled up. For instance, if memory addresses from 0 to 06000000 (6 million) are specified, the program will change the last address to 05773774.

If the ND-100 and the ND-500 share the memory: specify addresses from 0400000 and up. Remember that the TSB has room for not more than 01377 pages!

SINTRAN and no MM¶

Specify addresses from 0 and up. The size of the specified memory area should correspond to the number of pages reserved (each page holds 04000 bytes). If this area is too big, MEMIC will change the last address. The I2PA and D2PA registers will be set pointing to the first reserved memory page, and IUPL and DUPL will point to the last.

SINTRAN and MM off¶

The addresses specified should correspond to the pages reserved, with the first address pointing to the address of the first page, and the last address pointing to the last page (multiply the page numbers by 04000). If any of the specified addresses point outside the memory area reserved, MEMIC will change them.

SINTRAN and MM on¶

Specify addresses from 0 and up. The size of the specified memory area should correspond to the number of pages reserved. If this area is too big, MEMIC will change the last address. Address 0 will point to the first reserved memory page, and the TSB will be initiated for the reserved pages. If too much memory is specified (the TSB is filled up), the last address will be changed by MEMIC.

MEMIC may also run without memory. If the maximum memory addresses are specified as 0, only the cache will be used. In that case, memory need not be reserved when MEMIC runs under SINTRAN. When the machine has memory management, this should be off when running without memory. If not, a lot of misleading error messages will appear.

MEMIC asks for maximum control store address. The answer must be different from zero, i.e., 02000, 010000, or anything else suitable.

MEMIC then asks for the first control store address. The answer must be less than the maximum address. If it is nonzero, the micro programs will be relocated when they are loaded. The micro programs are always loaded from the first control store address.

MEMIC asks for stop on full page. If you want the program to pause when 22 lines have been written on the terminal, you should type Y, otherwise N. Stop on full page is useful when you are using a screen terminal.

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MEMIC - the ND-500 Cache and Memory Test Program¶

MEMIC asks for the last and first instruction memory addresses. Memory addresses occupy 25 bits. The first address must be less than the last. MEMIC will set the two last bits in both addresses to zero, to get addresses at word boundary. The two addresses might be given as for instance 0 and 0100000. If the last address is given as 0, the instruction memory will not be tested (The cache memory will be tested. The HIC bit will be set to 1, meaning Hit In Cache. All memory references will be forced to go to the cache, and therefore not use the memory at all.)

MEMIC then asks for the last and first data memory address. The answers follow the rules for the instruction memory questions.

MEMIC then asks for the number of instruction and data cache modules. The answer to both these questions is a single digit: 0, 1, 2, or 4. If the answer is 1 or 2 or 4, MEMIC will print the corresponding last cache address and ask if the user wants to change this last address. If the answer is Y, MEMIC asks for the new last address. This can be useful if only part of the cache memory is wanted (for instance if the user wants to avoid using a specific address bit). If the answer is 0, only the memory (and not the cache memory) will be tested. The program will set the don't-use-cache bit in the memory modus register.

MEMIC then asks whether the program is to be run with memory management or not. If memory management exists, MEMIC asks if it is to be on or off. After this question, an initiation micro program is run. It will clear the cache, set some registers, and, if the MM is on, fill the TSB (translation speed-up buffer). If necessary, MEMIC will change the memory addresses specified by the user.

MEMIC asks: TEST, VERIFY, OR BOTH? If the answer is T, only the first two routines will be run. If the answer is V, all routines except the first two will be run. If the answer is B, all routines are run.

MEMIC then asks whether information is wanted. If the answer is Y, a list, describing the two modes and the break characters, is printed.

MEMIC then asks whether all routines are to run in succession, or one by one. If the answer is the letter O, MEMIC will ask if error messages are wanted, and for the number of the test. The test routine with the specified number will then be run repeatedly. If the answer was A, all routines will be run in succession, one after the other. After the answer to this question, the memory initiation micro program is always run.

At last, MEMIC asks whether the tests 4 to 7 should check memory and cache parity or not. If the answer is Y, the memory status registers will be read and checked for every memory read. A side effect of this is that the IR register will not be used when parity checking, because TOONI/DOONI is loaded for every read.

The execution of the program may be interrupted and changed at any time by the typing of break characters.

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MEMIC - the ND-500 cache and memory test program¶

8.3. The test routines¶

8.3.1. TST01 Test EA (OPR(32-bits)-to-X#0-to-EA)¶

This is not a verification routine. It will ask for data or instruction memory. The answer is D or I. Then MEMIC will load a micro program and start it. ND-500 will then copy simulated OPR to the Effective Address register. OPR may be changed by the break character 0, or by F (flip switch) a bit in OPR. The user register is not used by this test.

8.3.2. TST02 Test data/instr. memory (OPR(32-bits)-to-memory)¶

This is not a verification routine. It will ask for data or instruction memory. The answer is D or I. Then it will request a memory address, load a micro program and start it. ND-500 will then write simulated OPR into the memory, in the specified address. The contents of the memory may be changed by the break characters 0 or F. The user register is not used by this test.

8.4. The verification routines¶

8.4.1. TST03 Verify address arithmetic¶

A micro program with ten different address arithmetic tests is loaded. Then the first test is started. It uses 200 different patterns, and also the complement of the patterns. Errors are reported back to ND-100 by DMA transfers. When one test is completed, the next is started, until all the ten tests are done. The following address arithmetic modes are tested:

PASSAA AA,DP1
PASSAA AA,DP2
PASSAA AA,FA1
PASSAA AA,FA2
PASSAB AB,IX
PASSAB AB,Z1X
PASSAB AB,4IX
PASSAB AB,8IX
PASSAB AB,1/8IX
PASSAB AB,B
PASSAB AB,R
PASSAB AB,PC
PASSAB AB,DPARG
AA+AB AA,FA1 AB,B
AA+AB AA,FA2 AB,R
A,SP
A,P

The user register displays test number. It counts from 0 to 011.

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MEMIC - the ND-500 Cache and Memory Test Program¶

8.4.2. TST04 Verify Data Memory (Address in Address)¶

This routine verifies the data memory, if any. ND-500 will store word address in word address in the specified memory area, and then read it back. If errors are detected, or the reading is complete, ND-500 unlocks. ND-100 checks the results and prints error messages where applicable. Memory reading and writing are done in two ways, sequentially and randomly. Sequentially means that the memory write and read starts at a minimum address, is incremented by 4, and ends at a maximum address. Randomly means that the addresses occur in this sequence: minimum, maximum, minimum+4, maximum-4, minimum+010, ...

There are four runs:

Run	Operation
0	Write sequentially, read sequentially
1	Write sequentially, read randomly
2	Write randomly, read sequentially
3	Write randomly, read randomly

In addition, when writing randomly, the micro program does 4 writes by consecutive micro instructions in order to stress the memory. When reading from the memory (and/or the cache), the registers DSTS0, DSTS1, and DSTS2, are read and checked, if parity check is requested. The user register displays run number.

8.4.3. TST05 Verify Data Memory (Compl. of Address in Address)¶

This routine is similar to the previous one. The difference is that the complement of word address is stored.

8.4.4. TST06 Verify Instruction Memory (Address in Address)¶

This routine is similar to TST04 above. The difference is that it verifies the instruction memory, and checks the registers ISTS0, ISTS1, ISTS2.

8.4.5. TST07 Verify Instruction Memory (Compl. of Address in Address)¶

This routine is similar to TST05 above. The difference is that it verifies the instruction memory.

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MEMIC - the ND-500 cache and memory test program¶

8.4.6. TST08 Verify memory (write once and read five times)¶

This routine verifies both data and instruction memory. ND-500 will write into the memory 17 32-bit words over and over again. When the specified memory area is filled, ND-500 will read it 5 times. Errors will be reported to ND-100 by DMA transfers. When 5 reads are completed, the pattern will be rotate shifted one left, and the process is repeated. Altogether, the writing takes place 01040 times.

The user register displays the number of reads, 05240 per channel (if both channels are verified, the count will go to 012500).

8.4.7. TST09 Verify data read and write with 1, 2, 3, and 4 bytes¶

This routine verifies a memory area of the same size as the cache (never more than 0200000 bytes). The contents of this area will always be halfword address in halfword during this test. This means that the first halfword will contain 0, the next will contain 2, the next 4, and so on. ND-500 first writes this area full, 4 bytes at a time, and reads it back, 4 bytes at a time. Next, ND-500 reads back 1 byte at a time, 2 bytes at a time, and 3 bytes at a time. Errors are reported to ND-100. After this, ND-500 writes halfword address in halfword address three times more, but now it writes 1 byte, 2 bytes, and 3 bytes at a time. Each time the whole area is written, it is read back 4 bytes at a time and checked, and errors are reported to ND-100. ND-100 waits for unlock, and prints error messages where applicable.

The user register is not used in this test.

8.4.8. TST10 Verify data cache directory¶

The specified memory area is first written with word address in word. After this, the memory contents is read back in such a way that the cache directory bits are checked. An example will clarify this: If the first memory address is specified as 0, and the number of bytes in the cache is 0100000 (two cache modules), then the memory read addresses will be in this sequence:

0, 0100000, 0, 0200000, 0, 0300000, 0, ... ,
4, 0100004, 4, 0200004, 4, 0300004, 4, ... ,

and so on.

The user register is not used in this test.

8.4.9. TST11 Verify instruction cache directory¶

This test is similar to the one above.

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PREFEF - the ND-500 prefetch processor test program.¶

9. PREFEF - the ND-500 prefetch processor test program.¶

9.1. General information.¶

PREFEF tests the prefetch processor. It loads instructions into the memory, and loads and starts small micro programs. These micro programs simulate macro program execution. They read and check the prefetch status register and the P register.

9.2. How to load and start the program.¶

Stand-alone: MASTER CLEAR. 1560&. *LOAD PREFEF.

SINTRAN: @RT PREFEF and possibly @LOG, or @STIMIC.

PREFEF asks for some parameters. These questions are similar to the questions asked by MEMIC. See the chapter on MEMIC.

9.3. The test routines.¶

9.3.1. TST01 Test prefetch clear and prefetch start.¶

The P register is loaded with zero. Then the micro program does prefetch clear and prefetch start. The micro program is restarted continually by master clear from ND-100.

9.3.2. TST02 Test prefetch clear, start, and continue.¶

The start address will be asked for. Then the micro program is loaded and started. It will load the P register with the specified start address, and then do prefetch clear, prefetch start, and prefetch continue. The micro program will be continually restarted by master clear from ND-100.

The user micro program (break character U) with the command L may be used to insert different macro instructions into the instruction memory prior to running this routine.

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PREF - the ND-500 prefetch processor test program¶

9.4. The verification routines¶

9.4.1. TST03 Verify execution of instructions with no operands¶

The memory is filled with instructions without operands, for instance NOOP. Then a micro program is loaded and started. It loads the P register, and does PRF,CLEAR and PRF,START and one PRF,PCONT for each macro instruction. It will read the prefetch status register and the P register after each PRF,PCONT. Errors are reported to the ND-100. Only one error is allowed for each macro instruction.
The user register will display the instruction under test.

9.4.2. TST04 Verify execution of instructions without operands, with register number¶

The memory is filled with instructions, for instance W1 CLR. Then a micro program is loaded and started. It will load the P register, do PRF,CLEAR and PRF,START and one PRF,PCONT for each macro instruction loaded into the memory. It will read and check the prefetch status register and the P register after each PRF,PCONT. Errors are reported to the ND-100. Only one error is allowed for each macro instruction.
The user register will display the instruction under test.

9.4.3. TST05 Verify execution of instructions with one operand¶

The memory is filled with instructions, for instance 'H3:=B.377:B. Then a small micro program is loaded and run. It will load the P register and do PRF,CLEAR and PRF,START and one PRF,PCONT for each macro instruction loaded into the memory. It will read and check the prefetch status register and the P register after each PRF,PCONT. Also, for some macro instructions, it will read and check a constant in A,DATA and an address (B+displacement) in B,FAL. Errors are reported to the ND-100. Only one error is allowed for each macro instruction.
The user register will display the instruction under test.

9.4.4. TST06 Verify execution of GO:B¶

The memory is filled with GO +6; GO -2 over and over again. Then a small micro program is loaded. It will start the macro program in address 2, check the results, and report errors where applicable. The most important check is that the P register is correct (2, 010, 6, 014, 012, 020, ...). Errors are reported to the ND-100. Only one error is allowed.
The user register is not used during this test.

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PREF - the ND-500 prefetch processor test program¶

9.4.5. TST07 Not yet implemented.¶

9.4.6. TST08 Verify execution of JMPMAP¶

The control store is filled with:

ALU, ADIR A, XD, SARG SLOW2 D, X#0 <addr> JMP LABEL,

where <addr> is the micro instruction's own address, and LABEL is the entry point of the verifying part of the micro program. A ND-500 macro instruction is fetched from a table, stored in the instruction memory and a small micro program starts it. The JMPMAP instruction in the micro program will jump to an entry point (a control store address), and this address will be loaded into X#0. X#0 is then verified against a table. This table contains approx. 1850 macro instructions. After all the legal macro instructions have been checked, it is checked that all the illegal macro instructions jump to a common entry point.

If this test is run in one-by-one mode, with maximum control store address equal to 01000, and the break character I is typed, the user can prepare a loop to use with the oscilloscope. Use maximum control address 010000, start the user micro program, and assemble JMP 0762,0; into address 0 and 01000. Start the user micro program in 0762. OPR may then be set with different instruction codes, and followed on the oscilloscope.

The user register will first contain a micro program load address. It will be incremented by 0100 as long as the micro program is loaded. When JMPMAP is checked, the user register contains a macro instruction table index. Afterwards, the user register contains an illegal instruction table index.

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PREFET¶

The ND–500 prefetch processor test program.

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ARITH - The ND-500 external arithmetic test program¶

10. ARITH - The ND-500 external arithmetic test program¶

10.1. General information¶

ARITH tests the external arithmetic. It does this by loading small micro programs that shift logical, arithmetical, and rotational. They also do floating add, subtract, multiply, and divide. The results are checked, and errors reported.

10.2. How to load and start the program¶

Stand-alone: MASTER CLEAR. 1560&. *LOAD ARITH.

SINTRAN: @RT ARITH and possibly @LOG, or @STMIC.

ARITH asks for some parameters. These questions are similar to the questions asked by SLICE. See the chapter on SLICE.

10.3. The test routines¶

10.3.1. TST01 Test logical shift¶

The routine will ask for two 32-bit numbers and a shift count. Then the first number is shifted logically. The number of positions to shift is specified by the shift count. Negative shift count is shift right, positive is shift left. Then the second number is shifted in the same way, and the whole process is repeated until a break character is typed. If the jump instructions in the micro program at addresses 5 and 012 are changed to NEXT; by the user micro program, the results will be output to the terminal.

10.3.2. TST02 Test arithmetical shift¶

This routine is similar to the previous one, but the shift is arithmetical (the sign bit is copied in right shifts).

10.3.3. TST03 Test rotational shift¶

This routine is similar to the previous two, but the shift is rotational, and the shift count should only be positive.

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ARITH - The ND-500 external arithmetic test program¶

10.3.4. TST04 Test single floating sum (A+B)¶

The program will ask for two numbers. Each is given either as a floating number or as two 16-bit octal numbers. Then a small micro program will add the two numbers repeatedly, first A+B, then B+A, and so on. If the jump instructions at addresses 5 and 012 are replaced with NEXT; by the user micro program, the results will be output to the terminal.

10.3.5. TST05 Test single floating diff (A-B)¶

This routine is similar to the previous one, except that it computes the difference, and not the sum.

10.3.6. TST06 Test single floating mult (A*B)¶

This routine is similar to the previous two, except that it computes the product of the two numbers.

10.3.7. TST07 Test single floating div (A/B)¶

This routine will compute A/B, but not B/A. Jump instructions at addresses 4, 010, 015, 021, and 026 may be replaced with NEXT; by the user micro program. The intermediate and final results will then be output to the terminal.

10.3.8. TST08 Test convert to floating¶

This routine will convert two 32-bit integers to floating. If the micro instructions at addresses 4, 010, 015, and 021 are changed to NEXT; by the user micro program, the results will be output to the terminal.

10.3.9. TST09 Test convert to integer¶

This routine will convert two floating numbers to integers. If the micro instructions at the addresses 5 and 012 are changed to NEXT; by the user micro program, the results will be output to the terminal.

10.3.10. TST10 Test single integer div (A/B)¶

This routine will convert two integers to floating, divide them, and convert the result back to integer. Jump instructions at addresses 4, 010, 015, 021, 026, 032, 037, 043, 050, 054, 061, 065, 072, 076 and 0103 may be changed to NEXT; by the user micro program in order to produce results on the terminal.

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ARITH - The ND-500 External Arithmetic Test Program¶

10.4. The Verification Routines¶

10.4.1. TST11 Verify Shift Logical with Shift Count as Argument¶

Shift logical is tested as word shift, halfword shift, and byte shift. Shift count is in the range 037 to -037, 017 to -017, or 7 to -7. For each type and shift count, a set of patterns is shifted, and the results are checked.
The user register displays shift count in bits 11-7, and a pattern number in bits 6-0.

10.4.2. TST12 Verify Shift Logical with Shift Count from Shift Count Register¶

This routine is similar to the previous one, except that it takes the shift count from the shift count register.

10.4.3. TST13 Verify Shift Arithmetical with Shift Count as Argument¶

This routine is similar to TST11 above. The only difference is that it checks arithmetical shift.

10.4.4. TST14 Verify Shift Arithmetical with Shift Count from Shift Count Register¶

This routine is similar to TST12 above. The only difference is that it checks arithmetical shift.

10.4.5. TST15 Verify Shift Rotational with Shift Count as Argument¶

This routine is similar to TST11 above, except that it checks rotational shift, and the shift count is in the range 037 to 0, 017 to 0, or 7 to 0.

10.4.6. TST16 Verify Shift Rotational with Shift Count from Shift Count Register¶

This routine is similar to TST12 above, except that it checks rotational shift. The shift count is only positive.

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ARITH - The ND-500 external arithmetic test program¶

10.4.7. TST17 Verify double floating sum.¶

Pairs of double floating numbers are added together, and the resulting sums are checked. The first part of this test consists of 63 numbers with only one bit in the mantissa (apart from the hidden bit). This number is added to itself, and the result should have the same mantissa, and an exponent incremented by one. The second part consists of a set of different patterns with given results to check against.
The user register will first display a bit number in the range 0 to 077, and then a pattern number.

10.4.8. TST18 Verify double floating diff.¶

This routine is similar to the previous one, except that it checks double floating difference.

10.4.9. TST19 Verify double floating mult.¶

Pairs of double floating numbers are multiplied together, and the results are checked.
The user register displays a pattern number.

10.4.10. TST20 Verify double floating div.¶

This routine is similar to the previous one, except that it checks double floating division. The divisions will be 1/(2n-1), where n is in the range 1 to 55 ( means exponentiation).

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NOMAN - the ND-500 no-memory-management test program¶

11. NOMAN - the ND-500 no-memory-management test program¶

11.1. General information¶

NOMAN tests the no-memory-management. Some machines are not equipped with memory management. NOMAN is intended for use on these machines.

A word of warning should be given here. NOMAN must not be run under SINTRAN on systems where the memory is shared and the ND-100 has no local memory (that is, address 0 for both the ND-100 and the ND-500 is the same memory word). If this were attempted, SINTRAN will be destroyed immediately.

11.2. How to load and start the program¶

Stand-alone: MASTER CLEAR. 15606. *LOAD NOMAN.

SINTRAN: @RT NOMAN and possibly @LOG, or @STIMIC.

NOMAN asks for some parameters. These questions are similar to the questions asked by MEMIC. See the chapter on MEMIC.

11.3. The test routines¶

11.3.1. TST01 Test no-memory-management registers¶

This routine loads and reads the registers DCINHL!, DCINHLJ, DZPA, DUPL, or ICINHL!, ICINHLJ, IZPA, IUPL. They are loaded with the value of OPR. This value may be changed at any time by using the break character 0.

11.4. The verification routines¶

11.4.1. TST02 Verify DCINHL!-DCINHLJ-DZPA-DUPL¶

These four 14-bit registers are loaded with all possible values. After each load, the values are read back and checked. The user register displays the value loaded.

11.4.2. TST03 Verify ICINHL!-ICINHLJ-IZPA-IUPL¶

This routine is similar to the previous one, except that it checks the instruction registers.

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NOMAN - the ND-500 no-memory-management test program¶

11.4.3. TST04 Verify DRADDRM and DRADDRL.¶

This routine checks the data real address registers. DRADDRM is an 8-bit register, and DRADDRL is a 16-bit register. DRADDRM is the most significant part of the real address, and DRADDRL is the least significant part. The real address is a 24-bit physical (not logical) memory byte address. The most significant bit is missing. Real address is the sum of the logical address and 04000*DZPA. The routine writes in the memory with different logical addresses and different contents of DZPA. Then it reads the real address and checks it. The user register displays the value of DZPA.

11.4.4. TST05 Verify IRADDRM and IRADDRL.¶

This routine is similar to the previous one, except that it tests the corresponding instruction registers.

11.4.5. TST06 Verify cache inhibit for data memory.¶

This routine checks the data cache inhibit limit registers DCINHLL and DCINHLIU. First, both registers are set to zero, meaning no inhibit. Then 4096 words are written into the available cache in such a way that not two words belong to the same page (the first address is 0, and the address is incremented by 040004, 0100010, or 020000, depending on the number of cache modules installed). The contents of the written words are address in address. After this, DCINHLL and DCINHIU are loaded with test values, and 4096 words are written into the cache, containing complement of address in address. After this, all the 4096 words are read back and checked. The area with page numbers greater than DCINHLL and smaller than DCINHIU should contain address in address. If not, cache inhibit does not work. The rest of the area should contain complement of address in address. If not, cache inhibit is active outside the range specified. All this is repeated 4 times, in order to check all 14 bits of DCINHLL/DCINHIU (the 4 initial addresses are 0, 040000000, 0100000000, 0140000000). The user register displays the value 0 to 3 in bits 7-6, and a table index for test values ranging from 0 to 074 in bits 5-0.

11.4.6. TST07 Verify cache inhibit for instruction memory.¶

This routine is similar to the previous one. The only difference is that it checks the corresponding functions in the instruction channel.

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NOMAN - the ND-500 no-memory-management test program¶

11.4.7. TST08 Verify that read and write only affects the DZPA-DUPL area.¶

This routine tests the DZPA and DUPL registers. First, DZPA is loaded with 0, and DUPL with 037777. Then address in address is written into the available memory area. After this, DZPA and DUPL are loaded with test values, and complement of real address is written into the memory. Then DZPA and DUPL are reloaded with 0 and 037777, cache is cleared, and the contents of the memory is read and checked. The memory area with page numbers lower than DZPA, or with page numbers greater than DUPL, should contain address in address. If not, DZPA and/or DUPL did not work properly. The rest of the memory should contain complement of address in address. If not, DZPA and/or DUPL failed. Please observe that this test uses cache clear. If cache clear does not work, this test will fail. TST10 will check cache clear. If run with a memory size of 010000000 (ten million octal) bytes, this test will take approx. 2 hours 10 minutes. The user register is not used by this test.

11.4.8. TST09 Verify that read and write only affects the IZPA-IUPL area.¶

This routine is similar to the previous one, except that it checks the corresponding functions in the instruction channel.

11.4.9. TST10 Verify data cache clear.¶

This routine checks that data cache clear works. The cache has 4 partitions, and any combination of these 4 may be cleared. First, the program selects an area of available data memory twice the size of the available cache. This memory area is thought to be divided in 8 parts, parts 0-7. DZPA is then made to point to the first page in part 0, and DUPL is made to point to the last page in part 7. Then the memory area is filled with address in address, written from the highest address to the lowest. After this, DZPA is made to point to the first page in part 4. Cache is not cleared. Part 0 to 3 of the memory is read, and it is checked that it really contains addresses for part 0 to 3. Then cache is cleared, with an argument in the range 0 to 017. This means that any combination of cache partitions may be cleared. Then parts 0 to 3 are read once more. The contents should be addresses from part 4 or 0, 5 or 1, 6 or 2, 7 or 3, depending on if the cache is cleared or not. If cache is cleared, the contents should come from part 4 to 7. The user register displays the cache clear argument (0-017).

11.4.10. TST11 Verify instruction cache clear.¶

This routine is similar to the previous one, except that it checks instruction cache clear.

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NOMAN¶

the ND-500 no-memory-management test program.

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GMOFF - the ND-500 memory-management-off test program¶

12. GMOFF - the ND-500 memory-management-off test program¶

12.1. General information¶

GMOFF tests the memory management, with memory management turned off. Some machines are not equipped with memory management, but the majority are. GMOFF is intended for use on those that are so equipped.

12.2. How to load and start the program¶

Stand-alone: MASTER CLEAR. 1560&. *LOAD GMOFF.

SINTRAN: @RT GMOFF and possibly @LOG, or @STIMC.

GMOFF asks for some parameters. These questions are similar to the questions asked by MEMIC. See the chapter on MEMIC.

12.3. The test routines¶

12.3.1. TST01 Not yet implemented¶

12.3.2. TST02 Dump routine for IWIPGU/DWIPGU¶

Both for instructions and data, there are two buffers, written-in-page (WIP) and page-used (PGU). Each of these buffers (4 altogether) contains 16384 bits. Each bit represents a page in the memory. These bits may be dumped on the terminal by this routine. 8 16-bit words (broadsides) are printed on each line. The bit for the smallest page number is in bit 0 of the leftmost word, and the bit for the greatest page number is in bit 15 of the rightmost word. The broadside number of the first 16 bits on a line is printed first on the line.

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GMOFF - the ND-500 memory-management-off test program.¶

12.4. The verification routines.¶

12.4.1. TST03 Verify data scratch file (DSCFA and DSCRF).¶

The 16 16-bit words in the scratch file are written, each separately, and then read back and checked. After this, all 16 words are written using the automatic incrementation of DSCFA, and then read back and checked.
The user register will display a scratch file word number in the range 0-017.

12.4.2. TST04 Verify instr. scratch file (ISCFA and ISCRF).¶

This routine is similar to the previous one. It checks the instruction scratch file.

12.4.3. TST05 Verify DLADDR and DRADDR.¶

The data memory is referenced (read 4 bytes). After this, the logical and real address registers are read and checked (they should be equal, except that the real address is shifted 1 to the right).
The user register displays the logical address.

12.4.4. TST06 Verify ILADDR and IRADDR.¶

This routine is similar to the previous one. It checks the instruction logical and real address registers.

12.4.5. TST07 Verify WIP-buffer for data memory (DWIPGU).¶

The WIP buffer for data memory is filled with a data pattern. After this, the pattern is read back and checked. Several different patterns are used.
The user register will contain 0 during this test.

12.4.6. TST08 Verify PGU-buffer for data memory (DWIPGU).¶

This routine is similar to the previous one. It checks the PGU buffer for data memory.

12.4.7. TST09 Verify WIP-buffer for instr. memory (IWIPGU).¶

This routine is similar to the previous one. It checks the WIP buffer for instruction memory.

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GMOFF - the ND-500 memory-management-off test program¶

12.4.8. TST10 Verify PGU-buffer for instr. memory (IWIPGU).¶

This routine is similar to the previous one. It checks the PGU buffer for instruction memory.

12.4.9. TST11 Verify WIP and PGU for data memory write and read (HIC=1).¶

The data memory is written into and read from, over the whole address range. The HIC bit is set to 1 in this test, to ensure that Sintran will not be destroyed (only the cache is used). As a result of this, patterns of bits should be 1 in WIP and PGU. These buffers are then read and checked.

The user register is not used in this test.

12.4.10. TST12 Verify WIP and PGU for instr. memory (HIC=1).¶

This routine is similar to the previous one. It checks the instruction memory.

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Page 91¶

GMOFF¶

the ND-500 memory-management-off test program.

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Page 92¶

GMEMT - the ND-500 Memory-Management-On Test Program¶

13. GMEMT - the ND-500 Memory-Management-On Test Program¶

13.1. General Information¶

GMEMT tests the memory management, with memory management turned on. Some machines are not equipped with memory management, but the majority are. GMEMT is intended for use on those that are so equipped.

13.2. How to Load and Start the Program¶

Stand-alone: MASTER CLEAR. 1560&. *LOAD GMEMT.

SINTRAN: @RT GMEMT and possibly @LOG, or @STMIMC.

GMEMT asks for some parameters. These questions are similar to the questions asked by MEMIC. See the chapter on MEMIC.

13.3. The Test Routines¶

13.3.1. TST01 Test Hashed TSB¶

This is a routine for accessing the memory with memory management on. It is both for instruction and data memory. TST01 asks for all relevant parameters. Based on these parameters, the hashed index is computed in the same way as the hardware will do, and printed on the terminal. If the user wants another index, the parameters will be asked for once more. After this, a microprogram is loaded and started. It will run in a loop until stopped. It will do the following:

Enable the TSB for write.
Clear the TSB and wait until the clear is finished.
Enable the TSB for read.
Load the process, segment, and domain registers.
Load the memory modus register.
Do a clear-block (bit 3 in DCON1/ICON1).
Read from the memory (address in X#0).
Read the status and put it in X#1 (should give TSB fault).
Enable the TSB for write.
Insert a page number into the TSB.
Enable the TSB for read.
Do a clear block.
Read from the memory.
Read the status and put it in X#2 (should not give TSB fault).
Read the real address and put it in X#3.
Read the hardware computed hashed index and put it in AL#1.
Repeat the whole sequence.

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GMEMT - the ND-500 memory-management-on test program.¶

13.3.2. TST02 Dump routine for IWIPGU/DWIPGU.¶

This is the same dump routine as TST02 under GMOFF.

13.3.3. TST03 Test sequential TSB (hash index = 0).¶

This routine is somewhat similar to TST01, but it will test the sequential part of the TSB, instead of only the hashed part. The routine inserts one entry in the hashed part of the TSB, with hash index equal to zero. After this, the memory is accessed three more times, with hash index equal to zero, but with other parameters. The next three entries, therefore, will go into the sequential part of the TSB. The routine will do the following:

Enable the TSB for write.
Clear the TSB and wait until the clear is finished.
Enable the TSB for read.
Load the process, segment, and domain registers, all with 0.
Load the memory modus register and do a clear block.
Load the X#3 register with 010,0.
Read from the memory, address in X#3.
Read the status to IODOUT (should give TSB fault).
Enable the TSB for write.
Insert a page number into the TSB.

After this, the first entry in the hashed part of the TSB holds a page number. Then the memory is accessed three times more, and the sequential part of the TSB will be used. Only the first of the three follows below:

Load ISTTSB/DSTTSB with 0. This means that the sequential part of the TSB is empty, as ISTTSB/DSTTSB always points to the first free entry. (The next two times, load with 1 and 2.)
Enable the TSB for read.
Activate FAS2. This makes the use of the sequential TSB possible.
Load the process register with 1, and the segment and domain registers with 0. (The next time, load the process register with 2, and the last time load with 4.)
Load the memory modus register and do a clear block.
Read from address 0.
Read the status to IODOUT (should give TSB fault).
Enable the TSB for write. Insert a page number (0100, 0101, 0102) in the (sequential) TSB.
Read the sequential TSB pointer (IHXA/DHXA) to AL#1 (or AL#2 or AL#3).
Repeat two more times, then do all of it again.

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GMEMT - the ND-500 memory-management-on test program.¶

13.4. The verification routines.¶

13.4.1. TST04 Verify the hash addressed TSB for data memory (DTSB).¶

This routine will fill the 512 entries of the TSB, and check the memory management status and the real address. The values of the process, segment, and domain registers are taken from a table, together with the logical address. The routine executes the following steps:

Clear the TSB. Read from the memory with the values from the 512 entries of the table, and insert page numbers 0 to 0777. Check the memory management status (TSB-fault should occur).
Read from the memory once more with the values from the table. Check the memory management status (TSB-fault should not occur), the real address, and the hardware computed hashed TSB index (remember, the most significant of the 9 bits is not checked).
As step 1, but some of the values from the tables are ones-complemented, and the page numbers to be inserted go from 037777 to 037000. In this way, all the bits in the TSB will get both the values 0 and 1.
As step 2, with some values ones-complemented.
As step 1, but with some other values ones-complemented.
As step 2, but with some other values ones-complemented.

The user register will display the following values: the value 0 to 5 in bits 14-12, and an index in bits 11-0.

13.4.2. TST05 Verify the hash addressed TSB for instr. memory (ITSB).¶

This routine is similar to the one above, except that it checks the instruction part.

13.4.3. TST06 Verify the sequential addressed TSB for data memory (DTSB).¶

This routine is somewhat similar to TST04, but it checks the sequential part of the TSB. It has the same 6 steps. It will read from the memory 257 times per step. All hashed indexes will be 0, because of the 257 different values taken from a table. This table is made in such a way that all the entries give the same hashed index, namely 0. The first access goes to the hashed part of the TSB, and the next 256 go to the sequential part of the TSB, since they have the same hashed index, and since FAS2 is enabled. The status, real address and sequential TSB pointer are checked.

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QMNT - the ND-500 memory-management-on test program.¶

13.4.4. TST07 Verify the sequential addressed TSB for instr. memory (ITSB).¶

This routine is similar to the one above, except that it checks the instruction part.

13.4.5. TST08 Verify data cache clear.¶

This routine checks that data cache clear works. The cache has 4 partitions, and any combination of these 4 may be cleared. First, the program selects an area of available data memory twice the size of the available cache. This memory area is thought to be divided in 8 parts, parts 0-7. Then the TSB is initiated for memory parts 0-7 with domain number 0, and for memory parts 4-7 with domain number 077 (63). In the first initiation, the first logical address is made to point to part 0. In the second initiation, the same first logical address is made to point to part 4. In this way, the same logical address will be translated to two different real addresses, dependent upon the value of the domain register. Now the memory area is filled with address in address, written from the highest address to the lowest, and domain number 0 is used. After this, the domain number is set to 077. Cache is not cleared. Part 0 to 3 of the memory is read, and it is checked that it really contains addresses for part 0 to 3. Then cache is cleared, with an argument in the range 0 to 017. This means that any combination of cache partitions may be cleared. Then parts 0 to 3 are read once more. The contents should be addresses from part 4 or 0, 5 or 1, 6 or 2, 7 or 3, depending on whether the cache is cleared or not. If cache is cleared, the contents should come from part 4 to 7. The user register displays the cache clear argument (0-017).

13.4.6. TST09 Verify instr. cache clear.¶

This routine is similar to the previous one, except that it checks instruction cache clear.

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TRAPT - the ND-500 trap system test program.¶

14. TRAPT - the ND-500 trap system test program.¶

14.1. General information.¶

TRAPT tests the trap system, using the registers S1, S2, and TE.

14.2. How to load and start the program.¶

Stand-alone: MASTER CLEAR. 1560&. *LOAD TRAPT.

SINTRAN: @RT TRAPT and possibly @LOG, or @STMIC.

TRAPT asks for some parameters. These questions are similar to the questions asked by MEMIC. See the chapter on MEMIC.

14.3. The test routines.¶

14.3.1. TST01 Not yet implemented.¶

14.3.2. TST02 Not yet implemented.¶

14.4. The verification routines.¶

14.4.1. TST03 Verify S1 traps enabled by the TE register.¶

This routine will check all S1 traps that may be enabled by the TE (trap enable) register. First, S1 and S2 are set to zero, and one of the bits 9 to 29 (011 to 035) is set to 1 in TE (the trap is enabled). The trap system is turned on. Then the routine checks that no traps occur. After that, the routine will set (by software) one of the bits 9 to 29 in the S1 register to 1, and check that the trap occurs (whenever there is a trap, the micro program continues in micro address 0627). When this routine is run in one-by-one mode, it will ask for the number of the bit to test. If the user answers with a negative number, a list of all the bits will be printed.

The user register displays the number of the bit under test.

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TRAPT - the ND-500 Trap System Test Program¶

14.4.2. TST04 Verify S1 Traps Not Enabled by the TE Register¶

This test is similar to the previous one, except that TE register is set to zero. Only two bits are tested, bits 30 and 31 (036 and 037).

14.4.3. TST05 Verify S2 Traps¶

This routine is similar to the previous two. The difference is that it checks the S2 traps. The TE register is set to zero. Bits 0 to 11 (00 to 013) are checked.

14.4.4. TST06 Verify S1 Bit 5 and 6 (Zero and Carry, Integer Arithmetic)¶

This routine checks that bits 5 and 6 in S1 are set properly by hardware. Two equal numbers are subtracted, and the micro program checks that only the two bits 5 and 6 become 1 in S1. This is repeated about 2 million times. Before the test starts, the registers TE, S1, and S2 are all set to zero. The user register is not used in this test.

14.4.5. TST07 Verify S1 Bit 5 (Zero, Floating Arithmetic)¶

This routine is similar to the previous one. It subtracts two equal floating numbers from each other and checks that S1 contains 1 only in bit 5.

14.4.6. TST08 Verify S1 Bit 6 and 011 (Carry and Overflow)¶

This routine is similar to the previous two. A number is subtracted from an integer that has only one bit, the sign bit. The micro program checks that only bits 6 and 9 in S1 are 1.

14.4.7. TST09 Verify S1 Bit 7 (Sign, Integer Arithmetic)¶

One number is subtracted from another, the first being 1 greater than the second. The result should be -1. It is checked that S1 contains 1 in bit 7 only.

14.4.8. TST10 Verify S1 Bit 7 (Sign, Floating Arithmetic)¶

Two floating numbers are subtracted from each other. The first is one less than the second, giving the result -1.0. The micro program checks that bit 7 in S1 becomes 1.

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TRAPT - the ND-500 trap system test program¶

14.4.9. TST11 Verify S1 bit 010 and 6 and 5 (flag and carry and zero)¶

Two numbers are subtracted from each other, giving zero as a result. Then K,LIFZ is applied, setting the flag to 1. This is then checked.

14.4.10. TST12 Verify overflow trap (S1 bit 011)¶

S1 and S2 are set to zero, and bit 9 is set in TE. The trap system is turned on. Then the number which has a 1 next to the sign bit is added into itself. This should give overflow trap. The micro program checks that the trap has occurred. This is done about half a million times. When the micro program stops, it leaves the last S1 in the IODOUT register, where the ND-100 fetches it, and checks that bit 9 is 1. If there is no trap, S1 is also left in IODOUT, but bit 0 is set to one to indicate a missing trap. The user register is not used by this test.

14.4.11. TST13 Verify floating underflow trap (S1 bit 015)¶

This routine is similar to the previous one. Bit 13 in TE is set to 1. A very small floating number (0100,1) is multiplied by itself. The micro program checks that the trap takes place. When the micro program stops, after about half a million trys, ND-100 reads IODOUT and examines bit 0. If 1, there was a trap missing. If 0, ND-100 checks that bit 13 is 1.

14.4.12. TST14 Verify floating overflow trap (S1 bit 016)¶

A great floating number (077777,177777) is multiplied by itself, after bit 14 in TE has been set to 1. IODOUT is checked by the ND-100 as in the previous routine.

14.4.13. TST15 Verify single instruction trap (S1 bit 021)¶

Four NOOP instructions are loaded into the memory, and bit 17 in TE is set to 1. Then the program in the memory (the 4 NOOP's) is started. When the first instruction is finished, the micro program checks that trap has taken place. Error checking is done by the micro program and by the ND-100 as in the previous routines.

14.4.14. TST16 Verify branch trap (S1 bit 022)¶

Two instructions (JMPG ABSOLUTE) are loaded into the memory. Bit 18 is set to 1 in TE. The program is started. When the first instruction is completed, the micro program checks that the trap has taken place. S1 is checked by the ND-100.

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TRAPT - the ND-500 Trap System Test Program¶

14.4.15. TST17 Verify Address Trap Fetch (S1 bit 025)¶

Four NOOP's are loaded into the memory. TE bit 21 is set to 1. The lower limit register (LL) is loaded with the address of the first NOOP. The higher limit register (HL) is loaded with the address+4. D, SEHLIM is set to 1 (In this case, it could as well have been set to 0. See HL and LL.), and the program is started. When the first instruction has been completed, the micro program checks that the trap has occurred.

14.4.16. TST18 Verify Address Trap Read for Data Memory (S1 bit 026)¶

For no memory management:

Bit 22 in TE is set to 1. The LL register is loaded with the address+020. The HL register is loaded with the address. D, SEHLIM is set to 1. Then data is read from the address+040, and the micro program checks that the trap has occurred.

For memory management:

The logical address ADDR is set to a start value of 020000000 (twenty million).
The segment register will take all values from 0 to 037, D, SEHLIM will be either 0 or 1.
LL and HL will take the values ADDR-4, ADDR, ADDR+4.
For each set of values, data is read from the memory, and the micro program checks whether trap occurs or not, according to the rules laid down for the LL and HL registers (the limit registers).
When the uppermost 5 bits of ADDR are all zero, bits 4-0 of the segment register are used in their place in the comparison with LL and HL.
After each check, ADDR is increased by 020000000 (twenty million).
When ADDR becomes zero, the test is finished.

14.4.17. TST19 Verify Address Trap Write for Data Memory (S1 bit 027)¶

Bit 23 in TE is set to 1. The LL register is loaded with the address. The HL register is loaded with the address+040. D, SEHLIM is set to 0. Then data is written to address+020, and the micro program checks that the trap has occurred.

14.4.18. TST20 Verify Address Zero Access Trap for Instruction Fetch (S1 bit 030)¶

Bit 24 in TE is set to 1. Four NOOP instructions are loaded into address zero in the memory and started. When the first has been finished, the micro program checks that the trap has occurred.

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TRAPT - The ND-500 Trap System Test Program¶

14.4.19. TST21 Verify Address Zero Access Trap for Data Memory (S1 bit 030)¶

Bit 24 in TE is set to 1. Data is read from address zero. The micro program checks that the trap has occurred.

14.4.20. TST22 Verify Disable Process Switch Timeout (S1 bit 036)¶

The TE register is set to zero. The loop counter (LC) is set to 0400 (256). Then bit 4 in S1 (disable process switch) is set to 1. The timeout should take place after 256 micro cycles. The loop counter is now decremented every second micro cycle. If it becomes zero, no trap took place, and the error is reported to the ND-100. If a trap occurred, the micro program checks that the value of the loop counter is in the range 0174 to 0203. If not, the error is reported to the ND-100.

14.4.21. TST23 Verify Disable Process Switch Error (S1 bit 037)¶

The TE register is set to zero. Bit 4 in S1 (disable process switch) is set to 1, and then bit 9 in S2 is set to 1 (DFATL). This should give a trap. ND-100 checks that S1 (read from IODOUT) has a 1 in bit 31 (037).

14.4.22. TST24 Verify Index Scaling Error Trap (S2 bit 0)¶

The instructions W1:=B.0(R3) and NOOP are loaded into the memory. X#2 is loaded with a number with only one bit equal to 1, namely bit 30 (036). Then the program is started. When the first instruction is finished, the micro program checks if the trap has occurred.

When the micro program stops, it puts S2 in IODOUT for ND-100 to read. S2 has only 12 bits. The rest are set to 1 if there has not been any trap, and to zero if trap took place. This is the same for all routines that checks S2 traps.

14.4.23. TST25 Verify Illegal Instruction Code Trap (S2 bit 1)¶

Illegal instructions are loaded into the memory (octal value 001). Then the program is started, and when the first illegal instruction has been executed, the micro program checks for a trap.

14.4.24. TST26 Verify Illegal Operand Specifier Trap (S2 bit 2)¶

The memory is loaded with two instructions (W1:=0). Then the program is started, and when the first instruction is finished, the micro program checks for a trap.

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TRAPT - the ND-500 Trap System Test Program¶

14.4.25. TST27 Verify Activate-from-ND-100 Trap (S2 Bit 5)¶

The micro program does not reset activate (tag code 5) as all the other routines initially do. Trap should therefore occur. This is checked by the micro program, and by the ND-100, as usual, checking S2.

14.4.26. TST28 Verify Terminate-from-ND-100 Trap (S2 Bit 6)¶

The micro program starts by setting the loop counter to 0400 and by counting it down to zero. This is done in order to let the ND-100 have time to execute IOX TERM. After the delay, the micro program checks for a trap.

14.4.27. TST29 Verify IFAIL Trap (S2 Bit 010)¶

The micro program starts by doing a cache disable (bit 4 in ICON0). Then it enables all kinds of error traps in ICON1. A program is started in the memory. This should set some error bits in ISTS1, and these bits should give a trap.

14.4.28. TST30 Verify DFAIL Trap (S2 Bit 011)¶

Bit 4 is set to 1 in ICON0 (cache disable). Error traps are enabled in ICON1. Then data is read from the memory. This should set error bits in DSTS1, and these bits should give a trap.

14.4.29. TST31 Verify Processor Fault Trap (S2 Bit 013)¶

In the micro program, address 014, a jump to address 020015 is made. The micro program will continue in address 015, but bit 13 in the address should give processor fault trap.

If ND-500 has 02000 control store locations, processor fault will not occur. Instead, the program checks that control store parity error stops the micro program.

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EXTRA - the ND-500 extra test program¶

15. EXTRA - the ND-500 extra test program¶

15.1. General information¶

EXTRA will do some additional tests that there were no room for in the other test programs. The tests in EXTRA are mainly prefetch processor tests.

15.2. How to load and start the program¶

Stand-alone: MASTER CLEAR. 1560&. *LOAD EXTRA.

SINTRAN: @RT EXTRA and possibly @LOG, or @STIMIC.

EXTRA asks for some parameters. These questions are similar to the questions asked by MEMIC. See the chapter on MEMIC.

15.3. The test routines¶

15.3.1. TST01 Not yet implemented¶

15.4. The verification routines¶

15.4.1. TST02 Verify index counters¶

There are four 8-bit index counters. First, they are cleared by D, IOCLR, and the micro program reads all four and checks that they really are zero. Then they are incremented, one by one, by IADJ. After each increment, the four counters are read and checked. The user register is not used by this test.

15.4.2. TST03 Verify conversion (BYTH BYTW HWYW)¶

The number 04000000 (four million) is put in X#0. Then X#0 is converted in three different ways, and the results are put into X#1, X#2, and X#3. The results are then checked. After each check, X#0 is decremented by 1, and the test continues until X#0 is zero. The user register is not used by this test.

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EXTRA - the ND-500 extra test program¶

15.4.3. TST04 Verify conditional AIUJ.¶

Conditional AIUJ is checked by first setting COND,MZRO to true, and then using the AIUJ operations AIUJ,FZRO and F,FONE. The result is then checked. Next, the condition is set to false, and the same AIUJ operations are used and checked once more. The test is repeated 04000000 (four million) times. The user register is not used in this test.

15.4.4. TST05 Verify prefetch addressing modes.¶

28 of the 30 addressing modes described in the ND-500 Reference Manual are tested (see Survey of addressing modes). The two exceptions are DESC and ALT. The test is done in the following way:

The micro program starts by loading 30 macro instructions into the instruction memory. The data memory is written in such a way that every word contains its own address+020. Then execution is started at the first instruction memory address. After the execution of every macro instruction, the micro program checks EA1 and EA2, the data register, P, the result in one of the index registers, and the prefetch status register. If necessary, the constant register is also checked. If an error message occurs, the test is stopped at once (if multiple errors, only the first is reported). When the last macro instruction has been executed, a GO instruction brings the micro program back to the beginning again. This loop is executed 040000 times. The user register is not used by this test.

15.4.5. TST06 Verify W1:=DESC(B.0110:B) (R4).¶

The instruction memory is loaded with four macro instructions, and the data memory is loaded with the descriptor (array length and array address). Then execution is started. The micro program will check array length in the data register, logical index in ORB, descriptor address in EA1 and EA2, the P register, the prefetch status register, the address of the current array element (in EA1 and EA2), and the logical index after incrementation. If an error message occurs, the test is stopped at once. The array that the descriptor points to takes all of the specified data memory. Therefore, the bigger the data memory is, the longer the test will last.

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EXTRA - the ND-500 extra test program¶

15.4.6. TST07 Verify INIT, CALL, ENIS, RET¶

The instruction memory is loaded with the four macro instructions INIT, CALL, ENIS and RET. Then execution is started at the first instruction memory address. After all four macro instructions have been executed, the micro program checks the results.

For INIT:¶

The bottom-of-stack address in the displacement register.
The main-stack-demand in ORB.
The total-stack-demand in ORB.
The P register.

For CALL:¶

The subroutine address in the displacement register.
The number of arguments in ORB.
The argument address in EAL.
The P register.
The conditions CONOP, DATOP and ENIER.

For ENIS:¶

The stack-demand in ORB.

For RET:¶

The P register.

The test is repeated 65535 times.
The user register is not used by this test.

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EXTRA - the ND-500 extra test program.¶

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Page 106¶

ND-500 Micro Mnemonics¶

ND-500 micro mnemonics in alphabetical and numerical order

Appendix A¶

ND-500 micro mnemonics in alphabetical and numerical order

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ND-500 Micro Mnemonics¶

In Alphabetical and Numerical Order¶

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ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

LOCATE	TYPE	RF	REG	Z	-1	0	1	VALUE	Z	LEAST	SIGN	MOST	SIGN.
A	J	N	Z	A	A	A	A	A	Z	A	A	A	A
A	J	Z	Z	+	A	A	A	A	J	J	J	J	J
A	AR	N	Z	J	A	A	A	+	J	+	Z	Z	Z
A	AR	A	Z	J	A	A	A	*	Z	*	*	*	*
A	AR	N	Z	*	Z	J	A	J	*	J	Z	Z	Z

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ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Address	Mnemonic
0000000	AAI7
0000001	AAZ7
0000002	AMA0
0000003	AMA1
0000004	AMA2
0000005	AMA3
0000006	AMA4
0000007	AMA5
0000010	AMA6
0000011	AAA1
0000012	AAA2
0000013	AAA3
0000014	AAA4
0000015	AAA5
0000016	AAA6
0000017	AAA7
0000020	AAAZ
0000021	ABM1
0000022	ABM2
0000023	ABM3
0000024	ABM4
0000025	ABM5
0000026	ABM6
0000027	ABM7
0000030	ABMZ
0000031	ADA0
0000032	ADA1
0000033	ADA2
0000034	ADA3
0000035	ADA4
0000036	ADA5
0000037	ADA6
0000040	ADA7
0000041	ADAZ
0000042	ADM7
0000043	ADMZ
0000050	ADI7
0000051	ADIZ
0000060	AFAI
0000061	Afr
0000062	Afr
0000070	Cregerc
0000071	Cregercr
0000073	APSP Lesn

(...continues up to 0000377)

Note: Adjust table as necessary for full continuation and clarity.

Page 110¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Address	Hex	Mnemonic
000001	01	COMPL
000002	02	WRITE ADR & REG 1
000003	03	READ AD. & REG. UPPER 1
000004	04	ADD ADR. & REG. UPPER 1
000005	05	ADD ADR. & REG. UPPER 2
000006	06	WRITE ADR. & REG. 2
000007	07	WRITE ADR. & REG. UPPER 2
000010	08	COMPARE ALL
000011	09	REG. TO MEMORY
000012	0A	TEST REG.
000013	0B	COMPARE ADR & REG
000014	0C	SUBTRACT ADR & REG 1
000015	0D	SUBTRACT ADR & REG. UPPER 1
000016	0E	SUBTRACT ADR & REG. 2
000017	0F	SUBTRACT ADR & REG. UPPER 2
000020	10	HALT
000021	11	WAIT
000022	12	RESET
000023	13	CAM
000024	14	CAM (CACHE)
000025	15	INST MF
000026	16	INST MF (MEMORY)
000027	17	INST MF 2
000030	18	STOP
000031	19	SKIP
000032	1A	CONTINUE
000033	1B	NOP
000034	1C	RESUME
000035	1D	DEFINE MEMORY
000036	1E	DEFINE MAP
000037	1F	RETURN
000040	20	TRANSFER
000041	21	TRANSFER UPPER
000042	22	TRANSFER LOWER
000043	23	TRANSFER BLOCK
000044	24	TRANSFER BLK UPPER
000045	25	TRANSFER BLK LOWER
000046	26	ADDRESS CALL
000047	27	ADDRESS RETURN
000050	28	ADJUST
000051	29	ADJUST UPPER
000052	2A	CACHE ADDRESS
000053	2B	CACHE DATA
000054	2C	CACHE CONTROL
000055	2D	CACHE MODE
000056	2E	CACHE INSTRUCT
000057	2F	CACHE MATCH
000060	30	FETCH
000061	31	FETCH UPPER
000062	32	STORE
000063	33	STORE UPPER
000064	34	LOAD
000065	35	LOAD UPPER
000066	36	MOVE
000067	37	SWAP
000070	38	MOVE LONG
000071	39	SWAP LONG
000072	3A	COPY
000073	3B	COPY UPPER
000074	3C	EXCHANGE LONG
000075	3D	EXCHANGE
000076	3E	EXCHANGE UPPER
000077	3F	EXCHANGE LONG UPPER
000100	40	SHIFT
000101	41	SHIFT LEFT
000102	42	SHIFT RIGHT
000103	43	SHIFT LEFT ARITHM
000104	44	SHIFT RIGHT ARITHM
000105	45	ROTATE
000106	46	ROTATE LEFT
000107	47	ROTATE RIGHT
000110	48	NEGATIVE
000111	49	ADD
000112	4A	ADD ADR
000113	4B	ADD ADR UP
000114	4C	ADD ADR LOW
000115	4D	ADD ADR UPPER
000116	4E	ADD ADR UPPER UP
000117	4F	ADD ADR LOWER DOWN
000120	50	SUBTRACT
000121	51	SUBTRACT ADR
000122	52	SUBTRACT ADR UP
000123	53	SUBTRACT ADR LOW
000124	54	SUBTRACT ADR UPPER
000125	55	SUBTRACT ADR UPPER UP
000126	56	SUBTRACT ADR LOWER
000127	57	SUBTRACT ADR LOWER DOWN
000130	58	MULTIPLY
000131	59	DIVIDE
000132	5A	LOGICAL AND
000133	5B	LOGICAL OR
000134	5C	LOGICAL XOR
000135	5D	LOGICAL NOT
000136	5E	ARITHMETIC AND
000137	5F	ARITHMETIC OR
000140	60	ARITHMETIC XOR
000141	61	ARITHMETIC NOT
000142	62	PRIORITY ENCODE
000143	63	PRIORITY DECODE
000144	64	SIGNAL
000145	65	UPDATE
000146	66	DISCARD
000147	67	RETAIN
000150	68	PROTECT
000151	69	UNPROTECT
000152	6A	TRACE ENABLE
000153	6B	TRACE DISABLE
000154	6C	TRACE LINE
000155	6D	TRACE ADDRESS
000156	6E	TRACE DATA
000157	6F	TRACE CONTROL
000160	70	BREAK
000161	71	BREAK POINT
000162	72	BREAK SETUP
000163	73	MONITOR
000164	74	MONITOR SETUP
000165	75	MONITOR START
000166	76	MONITOR END
000167	77	DEBUG
000170	78	DEBUG START
000171	79	DEBUG STOP
000172	7A	DEBUG SETUP
000173	7B	HALT SETUP
000174	7C	HALT START
000175	7D	HALT STOP
000176	7E	TEST LONG
000177	7F	TEST SHORT
000200	80	IO START
000201	81	IO STOP
000202	82	IO READ
000203	83	IO WRITE
000204	84	IO CONTROL
000205	85	IO DATA
000206	86	IO STATUS
000207	87	IO CONFIGURE
000210	88	IO SETUP
000211	89	IO TEST
000212	8A	IO ENABLE
000213	8B	IO DISABLE
000214	8C	IO INITIALIZE
000215	8D	IO RESET
000216	8E	IO WAIT
000217	8F	IO READY
000220	90	POWER ON
000221	91	POWER OFF
000222	92	RESTART
000223	93	SHUTDOWN
000224	94	SHUTDOWN INITIATE
000225	95	SHUTDOWN COMPLETE
000226	96	SAFETY ENABLE
000227	97	SAFETY DISABLE
000230	98	SAFETY LOCK
000231	99	SAFETY UNLOCK
000232	9A	PERMISSION GRANT
000233	9B	PERMISSION REVOKE
000234	9C	PERMISSION QUERY
000235	9D	PERMISSION CHECK
000236	9E	MODE SWITCH
000237	9F	MODE READ
000240	A0	MODE WRITE
000241	A1	MODE TEST
000242	A2	SYNCHRONIZE
000243	A3	SYNCH INIT
000244	A4	SYNCH COMPLETE
000245	A5	SYNCH EXCEPTION
000246	A6	SYNCH RECOVERY
000247	A7	SYNCH LOG
000250	A8	LOG START
000251	A9	LOG STOP
000252	AA	LOG QUERY
000253	AB	LOG UPDATE
000254	AC	LOG RESET
000255	AD	LOG SAVE
000256	AE	LOG LOAD
000257	AF	LOG CLEAR
000260	B0	FAST MODE
000261	B1	SLOW MODE
000262	B2	PERF MON
000263	B3	PERF READ
000264	B4	PERF WRITE
000265	B5	PERF TEST
000266	B6	PERF ENABLE
000267	B7	PERF DISABLE
000270	B8	TEMP MON
000271	B9	TEMP READ
000272	BA	TEMP WRITE
000273	BB	TEMP SET
000274	BC	TEMP RESET
000275	BD	TEMP ENABLE
000276	BE	TEMP DISABLE
000277	BF	TEMP SENSOR
000300	C0	VOLT MON
000301	C1	VOLT READ
000302	C2	VOLT WRITE
000303	C3	VOLT SET
000304	C4	VOLT RESET
000305	C5	VOLT ENABLE
000306	C6	VOLT DISABLE
000307	C7	VOLT SENSOR
000310	C8	CURR MON
000311	C9	CURR READ
000312	CA	CURR WRITE
000313	CB	CURR SET
000314	CC	CURR RESET
000315	CD	CURR ENABLE
000316	CE	CURR DISABLE
000317	CF	CURR SENSOR
000320	D0	FAN MON
000321	D1	FAN READ
000322	D2	FAN WRITE
000323	D3	FAN SET
000324	D4	FAN RESET
000325	D5	FAN ENABLE
000326	D6	FAN DISABLE
000327	D7	FAN SENSOR
000330	D8	AIRFLOW MON
000331	D9	AIRFLOW READ
000332	DA	AIRFLOW WRITE
000333	DB	AIRFLOW SET
000334	DC	AIRFLOW RESET
000335	DD	AIRFLOW ENABLE
000336	DE	AIRFLOW DISABLE
000337	DF	AIRFLOW SENSOR
000340	E0	LIGHT MON
000341	E1	LIGHT READ
000342	E2	LIGHT WRITE
000343	E3	LIGHT SET
000344	E4	LIGHT RESET
000345	E5	LIGHT ENABLE
000346	E6	LIGHT DISABLE
000347	E7	LIGHT SENSOR
000350	E8	WATER MON
000351	E9	WATER READ
000352	EA	WATER WRITE
000353	EB	WATER SET
000354	EC	WATER RESET
000355	ED	WATER ENABLE
000356	EE	WATER DISABLE
000357	EF	WATER SENSOR
000360	F0	PRESSURE MON
000361	F1	PRESSURE READ
000362	F2	PRESSURE WRITE
000363	F3	PRESSURE SET
000364	F4	PRESSURE RESET
000365	F5	PRESSURE ENABLE
000366	F6	PRESSURE DISABLE
000367	F7	PRESSURE SENSOR
000370	F8	HUMIDITY MON
000371	F9	HUMIDITY READ
000372	FA	HUMIDITY WRITE
000373	FB	HUMIDITY SET
000374	FC	HUMIDITY RESET
000375	FD	HUMIDITY ENABLE
000376	FE	HUMIDITY DISABLE
000377	FF	HUMIDITY SENSOR

ND - 30.013.02

Page 111¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Mnemonic	Code	Operation	ALU	Notes
AADD	0000000001	Add	Yes
ABOR	0000000010	Or	Yes
AADDP	0000000011	Add with previous carry	Yes
ASUB	0000000100	Subtract	Yes
AMUL	0000000101	Multiply	Yes
ADIV	0000000110	Divide	Yes
AXOR	0000000111	Exclusive Or	Yes
ANOT	0000001000	Not	Yes
...	...	...	...	...
ZZEND	1111111111	End	No	Terminator

ND - 30.013.02

Page 112¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶


ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD
SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB
MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL
DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV
AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND
OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR
XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR
NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT

ND-30.013.02

Page 113¶

ND-500 Micro Mnemonics¶

Alphabetical and Numerical Order¶


AND	CLR	DATA	FADD	JMP	LDX	STOP	SUB	XOR			BIT	MASK	NEX	PWD	SBW	XORW		ABW	ATAN	CARR	CIRC	COLW	COMM	DIV	ECXR	EXP	LAW	LDXW	LDYW	LIN	LRX	MAX	MIN	NULL	PW	SCALW	SHIFT	SUN	SWAP	WG	ZRO
	ERR	FACT	IDLR	JPS	LN	SUBW	TEST		ADD			MASK	NEXW	SIN	SQR	STC	STMXW	ADC	BACK	DIVW		SHIFW	SINW		LSX	MINW	MULW	NXT	RX	SUMW	SWAPW	TAN	WCD			SCPW	SIGN	SWST	TGI		XOR

Page 114¶

ND-500 Micro Mnemonics¶

In Alphabetical and Numerical Order¶

Address	Mnemonic	Operation
000000	AAAAA	DOUBLE
000001	AAAAB	DOUBLE
000002	AAAAC	DOUBLE
000003	AAAAD	DOUBLE
000004	AAAAE	DOUBLE
000005	AAAAF	DOUBLE
000006	AAAAG	DOUBLE
000007	AAAAA	DOUBLE
000010	AAAAI	DOUBLE
000011	AAAAJ	DOUBLE
000012	AAAAK	DOUBLE
000013	AAAAL	DOUBLE
000014	AAAAM	DOUBLE
000015	AAAAN	DOUBLE
000016	AAAAO	DOUBLE
000017	AAAAP	DOUBLE
000020	AAAAQ	DOUBLE
000021	AAAAR	DOUBLE
000022	AAAAS	DOUBLE
000023	AAAAT	DOUBLE
000024	AAAAU	DOUBLE
000025	AAAAV	DOUBLE
000026	AAAAW	DOUBLE
000027	AAAAX	DOUBLE
000030	AAAAY	DOUBLE
000031	AAAAZ	DOUBLE
361	CEXNO	CARRY FROM STATUS
362	CEXNZ	CARRY FROM STATUS
363	CEXO	CARRY FROM STATUS
364	CEXZ	CARRY FROM STATUS
365	CLCZO	CARRY FROM ALU OUTPUT
366	CLCZZ	CARRY FROM ALU OUTPUT
...	...	...
420	W

Note: The table continues with similar entries, showing various mnemonics with their respective numerical codes and operations.

ND - 30.013.02

Page 115¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Code	A	L	L	E	A	S	T	...
000000	A	A	A	1	1	Z	E	N
000001	A	L	L	E	A	S	T	A
000002	A	L	L	E	A	S	T	Z
000003	A	L	L	E	A	S	T	Y
000004	A	L	L	E	A	S	T	C
000005	A	L	L	E	A	S	T	M
000006	A	L	L	E	A	S	T	I
000007	A	L	L	E	A	S	T	E
...	...	...	...	...	...	...	...	...
000755	N	Z	Z	Z	E	R	O	R

Additional Information¶

Legend: The table above illustrates the ND-500 micro mnemonics arranged alphabetically and numerically.
Note: See references to controls, stores, and registers on the right side indicating various operations and registers.

Page 116¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Code	Mnemonic Name
020000	COM ST. ORG. ADDRESS REG.
020001	COM ST. FIRST ADDRESS REG.
020002	ALT. 1
020003	ALT. 2
020004	ALT. 3
020005	ALT. 4
020006	ALT. 5
020007	ALT. 6
020010	ALT. 7
020011	ALT. 8
020012	ALT. 9
020013	ALT. 10
020014	ALT. 11
020015	ALT. 12
020016	ALT. 13
020017	ALT. 14
020020	ALT. 15
020021	VWP
020022	A
020023	B
020024	C
020025	D
020026	AX
020027	BX
020030	CX
020031	DX
020032	AXL
020033	BXL
020034	CXL
020035	DXL
020036	IMMR
020037	Q
020040	Z
020041	M
020042	N
020043	V
020044	W
020045	X
020046	Y
020047	S
020050	T
020051	U
020052	P
020053	PSW
020054	WPTR
020055	LVL
020056	TMA
020057	TMB
020060	IMCS
020061	CCB
020062	CDB
020063	CME
020064	CSC
020065	RNG
020066	FIL
020067	OPC
020070	GFA
020071	GTA
020072	GFF
020073	GTB
020074	GFC
020075	GFD
020076	NMI
020077	PFH
020100	EXTI
020101	EXTO
020102	INI
020103	INTI
020104	INTR
020105	GFH
020106	PI
020107	PO
020110	CO
020111	BO
020112	COA
020113	AAI
020114	AIN
020115	AOS
020116	EXPC
020117	REC. 9
020120	ID
020121	IDT
020122	STI
020123	STOM
020124	CIO
020125	PIR1
020126	PSP
020127	SSC
020130	PTR
020131	INSC
020132	FF
020133	ASL
020134	ARA
020135	ADS
020136	RETA
020137	WDC
020140	K0
020141	K1
020142	K2
020143	K3
020144	K4
020145	K5
020146	K6
020147	K7
020150	MLE
020151	ADD
020152	SUB
020153	EXIT
020154	AW
020155	MD
020156	DSU
020157	DIV
020160	ALU
020161	MUL
020162	SPC
020163	INC
020164	LR
020165	DSR
020166	CR
020167	EMASK
020170	BADL
020171	MOD
020172	OPL
020173	CF
020174	OPLII
020175	TBBC
020176	XOR
020177	LCR
020200	REC.
020201	STSET2
020202	RSET2
020203	LPIM
020204	EMA
020205	GTV
020206	LW12
020207	REG. 4
020210	REG. 5
020211	REG. 6
020212	REG. 7
020213	REG. 8
020214	AXT
020215	CNP
020216	ANA
020217	ANB
020220	ANR
020221	AND
020222	OR
020223	NOT
020224	ORR
020225	ORA
020226	AA
020227	AB
020230	AS
020231	SGN
020232	RCD
020233	AMI
020234	ZXY
020235	PSH
020236	POP
020237	STSB
020240	GSF
020241	SEGF
020242	GFA
020243	AF
020244	AG
020245	AH
020246	AI
020247	AJ
020250	AK
020251	AL
020252	AM
020253	AN
020254	AO
020255	AP
020256	AQ
020257	AR
020260	AS
020261	AT
020262	AU
020263	AV
020264	AW
020265	AX
020266	AY
020267	AZ
020270	BA
020271	BB
020272	BC
020273	BD
020274	BE
020275	BF
020276	BG
020277	BH
020300	BI
020301	BJ
020302	BK
020303	BL
020304	BM
020305	BN
020306	BO
020307	BP
020310	BQ
020311	BR
020312	BS
020313	BT
020314	BU
020315	BV
020316	BW
020317	BX
020320	BY
020321	BZ
020322	CA
020323	CB
020324	CC
020325	CD
020326	CE
020327	CF
020330	CG
020331	CH
020332	CI
020333	CJ
020334	CK
020335	CL
020336	CM
020337	CN
020340	CO
020341	CP
020342	CQ
020343	CR
020344	CS
020345	CT
020346	CU
020347	CV
020350	CW
020351	CX
020352	CY
020353	CZ
020354	DA
020355	DB
020356	DC
020357	DD
020360	DE
020361	DF
020362	DG
020363	DH
020364	DI
020365	DJ
020366	DK
020367	DL
020370	DM
020371	DN
020372	DO
020373	DP
020374	DQ
020375	DR
020376	DS
020377	DT
020400	DU
020401	DV
020402	DW
020403	DX
020404	DY
020405	DZ
020406	EA
020407	EB
020410	EC
020411	ED
020412	EE
020413	EF
020414	EG
020415	EH
020416	EI
020417	EJ
020420	EK
020421	EL
020422	EM
020423	EN
020424	EO
020425	EP
020426	EQ
020427	ER
020430	ES
020431	ET
020432	EU
020433	EV
020434	EW
020435	EX
020436	EY
020437	EZ
020440	FA
020441	FB
020442	FC
020443	FD
020444	FE
020445	FF
020446	FG
020447	FH
020450	FI
020451	FJ
020452	FK
020453	FL
020454	FM
020455	FN
020456	FO
020457	FP
020460	FQ
020461	FR
020462	FS
020463	FT
020464	FU
020465	FV
020466	FW
020467	FX
020470	FY
020471	FZ
020472	GA
020473	GB
020474	GC
020475	GD
020476	GE
020477	GF

ND - 30.013.02

Page 117¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Address	Mnemonic
0000	INDEX Q REG
0001	DECOAD
0002	IND X 0
0003	IND Y 0
0004	IND X Z
0005	EQUIL
0006	ARC SLL1A
0007	SLL7A
0008	J6
0009	ARC WAIT
0010	INDEX R E
0011	EXT JUL
0012	SKSLA
0013	FLAVEL
0014	ARC ORDER
0015	ARC NONE
0016	IND3
0017	T3040
0018	K929 Z
0019	FREELATHY
0020	DEC 9
0021	K LSUP
0022	ARC REQLA
0023	AIYRA
0024	DIREER
0025	ENKAM
0026	CLEFT A
0027	UPAK
0028	MARTRACE
0029	ARC MAVEL
0030	ARC MAVELU
0031	ARC MEET
0032	CIREER
0033	ARJUMP
0034	ARC CLEAR
0035	ARC MAJESTIC
0036	NEWKANDY
0037	REELY
0038	FOX
0039	CREATURE
0040	ARCADE1
0041	ARAB1A
0042	UNDEAD
0043	TWO IDM
0044	PAINFUL
0045	KALIB
0046	LOOP
0047	SMASHER
0048	AARON
0049	APLULA
0050	HAMSTER
0051	BOULDER
0052	COFFEE
0053	CAFE
0054	FEARED
0055	FEER
0056	JAMELLA
0057	LABEL
0058	PINEAPPLE
0059	JIM
0060	HUGO
0061	OLD TIMER
0062	FFLETCH
0063	BIG MAJOR
0064	LIL PEP
0065	CONVECT
0066	FILLELA
0067	TRAMPOLINE
0068	SPANN
0069	LATENT
0070	TARSCOR
0071	JUMMY
0072	KYLE
0073	PILLOW
0074	NIKSOR
0075	PALOOPA
0076	LAPLAP
0077	SURVIVOR
0078	CAT
0079	CATALOGUE
0080	FOTILLA

ND - 30.013.02

Page 118¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Code	Mnemonic
60010	JUMP TO SUBR
60011	JUMP TO TEMP
60020	JUMP TO LINK
60021	JUMP TO RELATIVE
60022	JUMP TO ADR. REG.
60023	JUMP TO MEMORY
60024	JUMP CONDITIONAL IF FALSE
60025	CALL MONITOR
60026	INTERRUPT CONTROL
60027	RESET INTERRUPT CONTROL
60030	INCREMENT MEMORY
60031	DECREMENT MEMORY
61000	SEND TO PERI.
61001	RECEIVE FROM PERI.
61003	SEND TO MON.
61004	SEND EXTENDED
61005	READ MEMORY
61006	WRITE MEMORY
61007	TRANSFER MEMORY
61010	SET IF EQUAL
61011	SET IF GREATER THAN
61012	SET IF LESS THAN
61013	FREE JOB
61014	COPY PERIPH.
61015	COPY MEM.
61016	READ ADR. REG.
61017	WRITE ADR. REG.
61020	READ INDEX
61021	WRITE INDEX
61022	ADD MEMORY
61023	SUBTRACT MEMORY
61024	SHIFT MEMORY
61025	ROTATE MEMORY
61026	BRANCH ON CONDITION
62000	ADD ILLEGAL OPCODE
62001	COMPARE ILLEGAL OPCODE
62002	BRANCH (IF TRUE)
62003	BRANCH (IF FALSE)
62004	COPY MEMORY TO MEMORY
62005	COPY MEMORY TO IO REG.
62006	COPY IO REG. TO MEMORY
62007	EXCHANGE OPERAND
62010	EXCHANGE INDEX REG
62011	EXCHANGE ADR. REG.
62012	EXCHANGE PC ON ADR.
62013	EXCHANGE ADR. ON PC
62014	JUMP TO ADR. REG.
62015	JUMP TO PC
62016	JUMP ON CONDITION
62017	JUMP ON CONDITION EXE.
62020	INPUT DATA
62021	OUTPUT DATA
62022	CHANGE CONTROL REGISTERS
62023	COPY MASTER TO SLAVE
62024	COPY SLAVE TO MASTER
62025	EXECUTE ON CONDITION
62026	EXECUTE ON CONDITION EXE.
62027	JAM CONDITION
62030	JAM CONDITIONAL
62031	JUMP CONDITIONAL
62032	JUMP CONDITIONAL IF TRUE
62033	JUMP CONDITIONAL IF FALSE
62034	RETURN FROM SUBR.
62035	RETURN FROM INTERRUPT
62036	RETURN FROM 1..
62037	SET ADR. REG.
62040	SET INDEX REG.
62041	TRANSFER BLOCK
62042	TRANSFER INDEX
62043	SWAP MASTER/slave
62044	KEEP SLAVE MASTER
62045	SIGN EXTENSION
62046	EXTENSION 0
62047	SET PERI. INFO
63000	SET REG. X
63001	SET REG. Y
63002	RETURN FORWARD
63003	RETURN BACKWARD
63004	SET IF NOT EQUAL
63005	SET IF NOT GREATER THAN
63006	SET IF NOT LESS THAN
63007	TORQUE EXCHANGE
63010	CHANGE ADR.
63011	CHANGE INDEX
63012	JUMP ADR.
63013	JUMP INDEX
63014	RETURN ADR.
63015	RETURN INDEX
64000	JUMP TO MASTER
64001	JUMP TO SLAVE
64002	JUMP TO NEXT ITEM
64003	JUMP TO PREV. ITEM
64004	JUMP TO LIST ITEM
64005	JUMP TO ID FIELD
64006	TRAP ILLEGAL OPCODE
64007	TRAP TO MONITOR
64010	TRAP TO SUPERVISOR
64011	TRAP TO USER
64012	TRAP TO STACK
64013	GET STACK ITEM
64014	GET NESTED STACK
64015	NESTED TO STACK
64016	DECREMENT STACK
64017	INCREMENT STACK

ND - 30.013.02

Page 119¶

ND-500 Micro Mnemonics¶

Alphabetical Order¶

Mnemonic	Binary Code	Description
AAA	0100000 00000	WRITE 8 BYTES 10 LO BA MEMORY
AABRQ	0100000 00001	READ 4 BYTES LO BA MEMORY
AABRZ	0100000 00010	SAVE Z REG
ADM	0100000 00011	ADD MOV SIGN OUTPUT
ALU	0100000 00100	MICROINST PW@CS
ALOW	0100000 00101	ALU ACTIVATE OUTPUT CS
AMZNNF	0100000 00110	CONTROL INSTR FINISH
AMZNNNF	0100000 00111	WAIT FOR MEM CYC FINISHED
AMZNFY	0100000 01000	FETCH MACHINE
BCR	0100000 01001	RESTORE BATTERY CONTROL
BRCZ	0100000 01010	BRANCH CYCLE STARTED
CEL	0100000 01011	CYCLE SEQ CIRCUIT SEQ
CLKM	0100000 01100	CYCLE ON INSTR
CLKSLW	0100000 01101	CYCLE IS SLOW
CMPAGN	0100000 01110	COUNT A LEFT
CONM	0100000 01111	CONTINUE MICROINSTRUCTION
ECHO	0100000 10000	SINGLE INSTR FINISHED
IALU	0100000 10001	FINISHED INSTR
INIT	0100000 10010	INIT COUNTER A
IOCEP	0100000 10011	INPUT CHAN MON
IP	0100000 10100	INPUT CHAN ACCEPT
LDCZ	0100000 10101	RELOAD CNT INSTR
LF	0100000 10110	LATES CODE FORM MGC
LOADA	0100000 10111	CYCLE IS THINKING
LTC	0100000 11000	BRANCH PROGRAM COUNT
LLC	0100000 11001	BRANCH L OFF OF INS
MEMI	0100000 11010	EXECUTE AND CONTROL CHN
MVGAB	0100000 11011	OUTPUT EMPTY
NIP	0100000 11100	CONTROL FRONT PANEL
PH1	0100000 11101	SINGLE INSTR IS LOW
RCS	0100000 11110	FINALLY FINISHED
FSM	0100000 11111	FINISHED FIN INST
SL1UV	0100001 00000	STEP AND LATCHER MOV
SOS	0100001 00001	INITIALIZE CN LOG
SV0	0100001 00010	COUNTER CNT MOVED
SV1	0100001 00011	SAVE COUNTER SAVE VALUE
SOSL	0100001 00100	SAVE PAST CYCLE CMP
TRANS	0100001 00101	MOVE FROM ALU TRANSFER
TX4	0100001 00110	LAST CYCLE XFER
TLK	0100001 00111	TAKE LATCHER

Numerical Order¶

Code	Mnemonic	Description
643	AMZNNNF	WAIT FOR MEM CYCLE FINISHED
644	AMZNNF	CONTROL INSTR FINISH
645	IOCEP	INPUT CHAN MON
646	PH1	SINGLE INSTR IS LOW
647	BCR	RESTORE BATTERY CONTROL
648	CLKSLW	CYCLE IS SLOW
649	IALU	FINISHED INSTR
650	NIP	CONTROL FRONT PANEL
651	RCS	FINALLY FINISHED
652	SL1UV	STEP AND LATCHER MOV
653	S1	COUNT A LEFT
654	SOS	INITIALIZE CN LOG
655	SOSL	SAVE PAST CYCLE CMP
656	FSM	FINISHED FIN INST
657	LDCZ	RELOAD CNT INSTR
658	MVGAB	OUTPUT EMPTY
659	TRANS	MOVE FROM ALU TRANSFER
660	TLK	TAKE LATCHER
661	ADM	ADD MOV SIGN OUTPUT
662	ALU	MICROINST PW@CS
663	REGDL	LATER FOR STRG
664	LOADA	CYCLE IS THINKING
665	LLC	BRANCH L OFF OF INS
666	MEMI	EXECUTE AND CONTROL CHN
667	CEL	CYCLE SEQ CIRCUIT SEQ
668	CLK	CYCLE ON INSTR
669	CFM	COUNTER CNT INSTR
670	CONM	CONTINUE MICROINSTRUCTION
671	COUNT	CYCLE PAST INS PLL
672	CLKM	CYCLE ON INSTR
673	MPCC	FINISH COL MAC SEQ
674	ECHO	SINGLE INSTR FINISHED
675	3PH	FETCH MACHINE
676	LINE	CONTROL INSTRUCTION
677	SEL1	SELECTING INSTRUCTION
678	S20	SYSTEM READY INST
679	TSTS	INITIALIZE SYSTEM TEST
680	WBKQ	DOUBLE MEM ACCESS
681	WBKZ	OPENING DOG APPE
682	WRAP	TIME RS STORE CNTW
683	OSTEP	FINISH UNIT COMPACT
684	PLC0	FIGS AFT REJECT SE
685	PLC1	STEM MORE MOV AW
686	SV0	COUNTER CNT MOVED
687	SV1	SAVE COUNTER SAVE VALUE
688	LTC	BRANCH PROGRAM COUNT
689	AABRQ	READ 4 BYTES LO BA MEMORY

ND - 30.013.02

Page 120¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Address	Mnemonic
721	MKES
722

EMBLE EXRT RESULT INTO CPU

* 000010,000010,000010,000010,000010,000010,000010,000010,000010

ND - 30.013.02

Page 121¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

	S FUNCT	ALU OPERATOR	B SOURCE	B SELECT THROUGH ALU	ALU	CARRY	L + CARRY	T + STATUS	D REGISTER	X REGISTER	Y REGISTER	ALU OPERAND	MISC	COMMENT
000000	0.1	A	A * B	A + B	C	CARRY*1	A * B	Z	WR	B	X	ACDP	B AS B	ADD ACC
000002	0.6	0	A	A * C	A * B	A + C				C	D			I
000004	0.1	A	ADD	DCONST	VOID	ADD EXIST	ADDITION_OPERATION	ALU	ALU
000010	0.1	ACDP	ACDP	NOR	ADD	NOR	Z		PTR					BIT
000010	0.0	A * C	A + B	0 (ALU)	0									0 COMMENT
000011	0.1	1	2	4	CARRY + K		ADDITION OPERATION	L	7	A
000012	1	A	C		2						Z			D SELECT
000015	4	5	6	7	8	9	A	B		C	D	E	F
000020	0	TRANSFER	MEMORY	INSTRUCTION	F	G	H	J	K	F	CARRY AS FORCED ONE	B	F STATUS	X
000027	1	A	ACDP	S	T	U	WX	Y	ZZZ	T A	B MEMORY	0	4	V
000030	3	2	1	0	FZ	ZX	K STATUS	9	8	7	6	5	4	3
000034	0.2	0			1 0 .	X	Y	Z	Z REG	Z ALU SW	B	YX	ALU OP	Z

ND - 30.013.02

Page 122¶

ND-500 Micro Mnemonics¶

In Alphabetical and Numerical Order¶

	No of Bytes in A	S T	Z	IX	ZX	IY	ZY	IZ	ZIZ	IZI	IZZ	ZC	BCD
AFLAG	-	-	-	-	-	-	-	-	-	-	-	-	-
ADEKO1	COUNZ	Z	-	Z	-	Z	-	Z	Z	Z	Z	ZC	BADC
ADD	REG .	L	L	L	L	L	L	L	L	L	L	L	L
ADDLY	NEGBIN	REG	.	L	L	L	L	L	L	L	L	L	L
ADLIT	LOWNUM	L	.	L	L	L	L	L	L	L	L	L	L
ADOUT	STOP	UP	3	UP	3	UP	3	UP	UP	UP	UP	UP	UP
ADR	BSEXT	L	.	L	L	L	L	L	L	L	L	L	L
ADRT	NEGNUM	TYPE	2	2	2	2	2	2	2	2	2	2	2
ADTOT	OFFGE	-	-	-	-	-	-	-	-	-	-	-	-

...

INST	CODE	PAGE	INST	CODE	PAGE	INST	CODE	PAGE
LD	000001	77643	POPW	000067	77745	RETI	000027	81605
LDIN	000002	77664	PUSHW	000071	77763	RETM	000030	81703
LDI	000003	77684	BRA	000072	80012	RET	000036	81726
					PUSH	000073	80112

...

ND - 30.013.02¶

Page 123¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Count	Most Sign.	Least Sign.	Binary
14	7	7	00000100 00000000
14	8	8	00001000 00000000
14	9	9	00001001 00000000
14	A	A	00001010 00000000
14	B	B	00001011 00000000
14	C	C	00001100 00000000
14	D	D	00001101 00000000
14	E	E	00001110 00000000
14	F	F	00001111 00000000
3	0	0	00000000 00000100
3	1	1	00000001 00000000
3	2	2	00000010 00000000
3	3	3	00000011 00000000
3	4	4	00000100 00000000
3	5	5	00000101 00000000
3	6	6	00000110 00000000
3	7	7	00000111 00000000

ND - 30.013.02

Page 124¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶


AAA AO	AFMC	ASHM	ADAL	AFMC	AFMC	CAF	IRD	MNZ	XERC		FL	CNME	HIR	MNZ	NMJ	LTTL	XERC		MNZ	FLAT	CNME
ATBAO	AFC	CNS	MAX	CRST	ZMOD	LEAR	IMI
MIND	ADC	HLW	BM	LATH		ANST	CDB
STRZ		AAA	MGMF	MCRD		DSCC	SCLR
MILLS	ZEN		SWI	USR	BODY	DDLD	CNME
COMME	INV	PLA	TRIM	CRM	szb	AMIX	UMC
PNTRS	ERRY	PWDP	ABTR	DDD	AFMC	MIND	SMCC
AFM	RID	ATE	AWH	OB	YR	YRT	TBSC	IH	ZBA	ATEO		BL	BL	ZOID	CLL	LEAR	0D	WRD	LTNR	ROA	BZ
36300	8070	BODY	MACR	RAFM	WKND	IW	ASHM	UOL	ERRY	AQ		AFM	FLAT	YR	7040	CRST	ODBC	BLRR	FLAT	FLYB	KM
3740	CAL	APO	SWI	IDA	IDI	LOL	IL		RAAA	NPO	MV	KKKK	LZW	PTF	MOD	REGN	ZZZ	YA	RRD	RID	assertTrue
AssertEqual	ISQR	YOB	ROW	XERC	EIC	XP	QAM		ZZZ	DD	MT	SRR	SWI	UMC	NMI	EIFL	ERL	LZW	DSTSQ	MTH	YMT
SCLN	SAM	LSSH	AM	FAL	CLLC	CCH	FL		RUM	AMG	EOH	LFW	DF	ERXN	AMAC	ZZZ	LE	NNN	FAAAAAAAAAAXYNZZZAAAY	A	FLT
LUT	FLAT	ROM	DEC	ATE	HASH		CMDB		TPSD	DZT	HAR	ZN	CTT	YAR	HKNN	KNOS	AU	UNK	HFL	IWL	KE

ND - 30.013.02

Page 125¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶


ABREG	Z	NDCHN	N
ABS	LAST SIGN.	F	MREG
ABS	MOST SIGN.	F	MTEC
ACASL		YMPT	Z
ACASU		YMPT	Z
ADD	FLOAT	F	FL
ADD	FIX. POINT	F	FN
AND	LAST SIGN.	F	NDCHN
AND	MOST SIGN.	F	NDCHN
AREA	LAST SIGN.	N	MREG
AREA	MOST SIGN.	N	MTEC
CFP		Y	1
CL		Y	1
EX	LAST SIGN.	N	NDCHN
INC	MOST SIGN.	F	NDCHN
INCH		N	MREG
JMP		STP	Z
JSEQ		STP	Z
LIA		Y	Z
LIG	LAST SIGN.	N	NDCHN
LIP	LAST SIGN.	N	NDCHN
LOP	MOST SIGN.	F	NDCHN
NEG		N	TLAP
LIG	MO. SIGN.	F	MTEC
PAU		ALL	INCP
PAU2		ALL	INP
PAUSE		INP4	Z
SJ	LAST SIGN.	N	NDCHN
SMU	MOST SIGN.	F	FL
SREG	SIGN		7
STOP		Z	1
WRA		TO	2

Code	Mnemonic
0000	WRA
0001	STOP
0002	SREG SIGN
0003	SMU
0004	SJ LAST
0005	PAUSE
0006	PAU2
0007	PAU ALL
0010	NEG
0011	LOP MOST
0012	LIP LAST
0013	LIG LAST
0014	LIG MOST
0015	LIA
0016	JSEQ
0017	JMP
0020	INCH
0021	INC MOST
0022	EX LAST
0023	CL
0024	CFP
0025	AREA MS
0026	AREA LS
0027	AND MS

ND - 30.013.02

Page 126¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Address	Mnemonic	Binary
0	Z BT MASK BIT 7	01001111
1	Z BT MASK BIT 6	01001110
2	Z BT MASK BIT 5	01001101
3	Z BT MASK BIT 4	01001100
4	Z BT MASK BIT 3	01001011
5	Z BT MASK BIT 2	01001010
6	Z BT MASK BIT 1	01001001
7	Z BT MASK BIT 0	01001000
10	Z EXTR R E	01000111
11	Z EXTMASK	01000110
12	Z CMP INTFC TO EXTL	01000101
13	Z LTC IRCON TOEREG	01000100
14	Z FIX SEGREG	01000011
15	Z NDX DO SPL OUT	01000010
16	Z NETWORK	01000001
17	Z MMV	01000000
0010000	Z INT TO	00010000
0010100	Z CMP INTFC TOER 01010100
0011100	Z DATA BACKUP Z DATA BUS REGISTER	00011100
0100000	Z DATA REGISTER	00000000
0100100	Z DIN	00001100
0101000	Z SIGN EXTEN	00010100
0110000	Z IRX DC	00100000
0140000	Z SCUL INT SBEG17	01100000
1400000	Z EXTMASK	00000110
1410000	Z INT TO BPH	00001101
1414401	Z CONTROL REG	00001110
1414404	Z MAIL REG	00011011
1414405	Z CONTROL REG 000101
1414406	Z BANK REGISTER	00101001
1414407	Z INT KIFA Z CK R SECU-U	00101100
s144 40	Z-1 SECUR-UP	0100111 1
s444041	Z-1 SAVE-UP	00010100
s444042	Z-SEG REG-DEF	00111100
s 444043	Z DEFU AG	01000001
s 444046	Z SCGR SEGREG	11100001

Page 127¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Binary	Mnemonic	Attribute	Comment
00000 00000 00000	ZMH	N	SYS MISC
00000 00000 00100	ZSC	N	SYS MICRO
00000 00000 01000	ZRD	ZRD	GENERAL
00000 00000 01001	ZDD	ZDD	EDIT
00000 00000 01010	ZLD	ZLD	LOAD
00000 00000 01011	ZSD	ZSD	STORE
00000 00000 01100	ZCD	ZCD	COMPARE
00000 00000 01101	ZID	ZID	IO
00000 00000 01110	ZMD	ZMD	MODIF
00000 00000 01111	ZCK	ZCK	CHECK
00000 00000 10000	ZHT	ZHT	HALT
00000 00000 10001	ZDS	ZDS	DISABLE
00000 00000 10010	ZIS	ZIS	ENABLE
00000 00000 10011	ZRC	ZRC	RESUME
00000 00000 10100	ZSR	ZSR	SETUP
00000 00000 10101	ZCC	ZCC	CONTROL
00000 00000 10110	ZTS	ZTS	TEST
00000 00000 10111	ZHT	ZHT	HALT
00000 00001 00000	ZPT	ZPT	PRINT
00000 00001 00001	ZAD	ZAD	ADD
00000 00001 00010	ZSU	ZSU	SUBTRACT
00000 00001 00011	ZMU	ZMU	MULTIPLY
00000 00001 00100	ZDV	ZDV	DIVIDE
00000 00001 00101	ZLR	ZLR	LOWER
00000 00001 00110	ZUP	ZUP	UPPER
00000 00001 00111	ZLE	ZLE	LESS
00000 00001 01000	ZGT	ZGT	GREATER
00000 00001 01001	ZEQ	ZEQ	EQUAL
00000 00001 01010	ZNE	ZNE	NOT EQUAL
00000 00001 01011	ZLN	ZLN	LINE
00000 00001 01100	ZSP	ZSP	SPACE
00000 00001 01101	ZBR	ZBR	BRANCH
00000 00001 01110	ZLB	ZLB	LONG BR
00000 00001 01111	ZSC	ZSC	SHORT COND
00000 00001 10000	ZLC	ZLC	LOOP COND
00000 00001 10001	ZSL	ZSL	SHIFT LEFT
00000 00001 10010	ZSR	ZSR	SHIFT RIGHT
00000 00010 00000	ZOR	ZOR	OR
00000 00010 00001	ZAN	ZAN	AND
00000 00010 00010	ZXO	ZXO	XOR
00000 00010 00011	ZCC	ZCC	CY CLE CL

ND - 30.013.02

Page 128¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

	DOUBLE	AM AEMBLER REG			LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	MOST	MOST	MOST	MOST	MOST	MOST
BET	STORE	A WREG AD JUSTMENT	ALTITUDE CONTROL	L SAFETY CHECK	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	LEAST	MOST	MOST	MOST	MOST	MOST	MOST	MOST	MOST	MOST	MOST	MOST	MOST
GET	STOP	A 1	2	3	4	5	L LINE ADDRESS	PARAMETERS INSTRUCTIONS	HEX UL A

000007, 000102, 000t03, 000005	000006, 000107, 000110, 000111	000112, 000113, 000114, 000115
2	3	4
5	6	7
10	11	12
argetter

7	7	7	7	7	N	N	7	N	N
2	2	2	2	2	2	Z	7	Z	Z

ND - 30.013.02

Page 129¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Mnemonic	Code
ADD MOST	00000000000
ADD S (A)	00000000001
ADDRESS	00000000010
AMOST	00000000011
AP OUT	00000000100
AP TEST	00000000101
AREG MOST	00000000110
AREG S (A)	00000000111
ATEST	00000001000
ATTR	00000001001
AVERAGE	00000001010
BNZ	00000001011
BP	00000001100
BP TEST	00000001101
CACHE REF	00000001110
CMOV	00000001111
CMOV APA	00000010000
CMOVS A	00000010001
COMBINE	00000010010
CONCAT	00000010011
COUNT	00000010100
DIV	00000010101
FAIL	00000010110
INSTR	00000010111
INTMEM	00000011000
IO READY	00000011001
JUMP	00000011010
LWU	00000011011
LWUWO	00000011100
MEM LWU	00000011101
MWA	00000011110
NEGATIVE	00000011111
NOT (M)	00000100000
NOT A	00000100001
NOT P	00000100010
NOT REL	00000100011
ONES	00000100100
POP CNT	00000100101
REV TRI	00000100110
SEQU	00000100111
SINGLE	00000101000
SKIP	00000101001
STORE (M)	00000101010
SUB MEM	00000101011
TIM OS	00000101100
UPSHIFT M	00000101101
WORD	00000101110
ZERO	00000101111

ND - 30.013.02

Page 130¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Address	Mnemonic	Binary Code
12654	CNOP,LC,W,CZ	0000000000000101
12655	CNOP,LC,W,CAN	0000000000000100
12656	CNOP,LC,W,COZ	0000000000001100
12657	CNOP,LC,W,CSZ	0000000000001101
12660	CNOP,SC,W,CZ	0000000000010101
12661	CNOP,SC,W,CAN	0000000000010100
12662	CNOP,SC,W,COZ	0000000000011100
12663	CNOP,SC,W,CSZ	0000000000011101
12664	CNOP,ZC,W,CZ	0000000000110101
12665	CNOP,ZC,W,CAN	0000000000110100
12666	CNOP,ZC,W,COZ	0000000000111100
12667	CNOP,ZC,W,CSZ	0000000000111101
12670	CNOP,SC,R,CZ	0000000001010101
12671	CNOP,SC,R,CAN	0000000001010100
12672	CNOP,SC,R,COZ	0000000001011100
12673	CNOP,SC,R,CSZ	0000000001011101
12674	CEND,FNC,LC	0000000001100000
12675	CEND,FNC,SC	0000000001100100
12676	CEND,FNC,ZC	0000000001101000
12677	CNAM,LC	0000000110000000
12678	CNAM,SC	0000000110000010
12679	CNAM,ZC	0000000110000100
12680	CNAM,XC	0000000110000110
12681	CNAM,YC	0000000110001000
12682	CNAM,BC	0000000110001010
12683	CNAM,CC	0000000110001100
12684	CNAM,DC	0000000110001110
12685	CNAM,EC	0000000110010000
12686	CNAM,FC	0000000110010010
12687	CNAM,GC	0000000110010100
12688	CNAM,HC	0000000110010110
12689	CNAM,IC	0000000110011000
12690	CNAM,JC	0000000110011010
12691	CNAM,KC	0000000110011100
12692	CNAM,LC	0000000110011110
12693	CNAM,MC	0000000110100000
12694	CNAM,NC	0000000110100010
12695	CNAM,OC	0000000110100100
12696	CNAM,PC	0000000110100110
12697	CNAM,QC	0000000110101000
12698	CNAM,RC	0000000110101010
12699	CNAM,SC	0000000110101100
12700	CNAM,TC	0000000110101110
12701	CNAM,UC	0000000110110000
12702	CNAM,VC	0000000110110010
12703	CNAM,WC	0000000110110100
12704	CNAM,XC	0000000110110110
12705	CNAM,YC	0000000110111000
12706	CNAM,BC	0000000110111010
12707	CNAM,CC	0000000110111100
12708	CNAM,DC	0000000110111110
12709	CNAM,EC	0000000111000000
12710	CNAM,FC	0000000111000010
12711	CNAM,GC	0000000111000100
12712	CNAM,HC	0000000111000110
12713	CNAM,IC	0000000111001000
12714	CNAM,JC	0000000111001010
12715	CNAM,KC	0000000111001100
12716	CNAM,LC	0000000111001110
12717	CNAM,MC	0000000111010000
12718	CNAM,NC	0000000111010010
12719	CNAM,OC	0000000111010100
12720	CNAM,PC	0000000111010110
12721	CNAM,QC	0000000111011000
12722	CNAM,RC	0000000111011010
12723	CNAM,SC	0000000111011100
12724	CNAM,TC	0000000111011110
12725	CNAM,UC	0000000111100000
12726	CNAM,VC	0000000111100010
12727	CNAM,WC	0000000111100100
12728	CNAM,XC	0000000111100110
12729	CNAM,YC	0000000111101000
12730	CNAM,BC	0000000111101010
12731	CNAM,CC	0000000111101100
12732	CNAM,DC	0000000111101110
12733	CNAM,EC	0000000111110000
12734	CNAM,FC	0000000111110010
12735	CNAM,GC	0000000111110100
12736	CNAM,HC	0000000111110110
12737	CNAM,IC	0000000111111000
12738	CNAM,JC	0000000111111010
12739	CNAM,KC	0000000111111100
12740	CNAM,LC	0000000111111110
12741	CNAM,MC	0000001000000000
12742	CNAM,NC	0000001000000010
12743	CNAM,OC	0000001000000100
12744	CNAM,PC	0000001000000110
12745	CNAM,QC	0000001000001000
12746	CNAM,RC	0000001000001010
12747	CNAM,SC	0000001000001100
12748	CNAM,TC	0000001000001110
12749	CNAM,UC	0000001000010000
12750	CNAM,VC	0000001000010010
12751	CNAM,WC	0000001000010100
12752	CNAM,XC	0000001000010110
12753	CNAM,YC	0000001000011000
12754	CNAM,BC	0000001000011010
12755	CNAM,CC	0000001000011100
12756	CNAM,DC	0000001000011110
12757	CNAM,EC	0000001000100000
12758	CNAM,FC	0000001000100010
12759	CNAM,GC	0000001000100100
12760	CNAM,HC	0000001000100110
12761	CNAM,IC	0000001000101000
12762	CNAM,JC	0000001000101010
12763	CNAM,KC	0000001000101100
12764	CNAM,LC	0000001000101110
12765	CNAM,MC	0000001000110000
12766	CNAM,NC	0000001000110010
12767	CNAM,OC	0000001000110100
12768	CNAM,PC	0000001000110110
12769	CNAM,QC	0000001000111000
12770	CNAM,RC	0000001000111010
12771	CNAM,SC	0000001000111100
12772	CNAM,TC	0000001000111110
12773	CNAM,UC	0000001001000000
12774	CNAM,VC	0000001001000010
12775	CNAM,WC	0000001001000100
12776	CNAM,XC	0000001001000110
12777	CNAM,YC	0000001001001000
12778	CNAM,BC	0000001001001010
12779	CNAM,CC	0000001001001100
12780	CNAM,DC	0000001001001110
12781	CNAM,EC	0000001001010000
12782	CNAM,FC	0000001001010010
12783	CNAM,GC	0000001001010100
12784	CNAM,HC	0000001001010110
12785	CNAM,IC	0000001001011000
12786	CNAM,JC	0000001001011010
12787	CNAM,KC	0000001001011100
12788	CNAM,LC	0000001001011110
12789	CNAM,MC	0000001001100000
12790	CNAM,NC	0000001001100010
12791	CNAM,OC	0000001001100100
12792	CNAM,PC	0000001001100110
12793	CNAM,QC	0000001001101000
12794	CNAM,RC	0000001001101010
12795	CNAM,SC	0000001001101100
12796	CNAM,TC	0000001001101110
12797	CNAM,UC	0000001001110000
12798	CNAM,VC	0000001001110010
12799	CNAM,WC	0000001001110100
13004	EPTRT,LC	0000000010000000
13005	EPTRT,SC	0000000010000100
13006	EPTRT,ZC	0000000010001000
13007	EPTRT,XC	0000000010001100
13008	EPTRT,YC	0000000010010000
13009	EPTRT,BC	0000000010010100
13010	EPTRT,CC	0000000010011000
13011	EPTRT,DC	0000000010011100
13012	EPTRT,EC	0000000010100000
13013	EPTRT,FC	0000000010100100
13014	EPTRT,GC	0000000010101000
13015	EPTRT,HC	0000000010101100
13016	EPTRT,IC	0000000010110000
13017	EPTRT,JC	0000000010110100
13018	EPTRT,KC	0000000010111000
13019	EPTRT,LC	0000000010111100
13020	EPTRT,MC	0000000011000000
13021	EPTRT,NC	0000000011000100
13022	F,FLAG	0000000011001000

ND - 30.013.02

Page 131¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Mnemonics Table¶

Code	Mnemonic
125	SAVE CD STATUS
126	SET EOD LEVEL
127	ST LATCH I
128	ST TIMER
129	ST LATCH T
130	Reserved
131	SAVE ALU
132	XFER STATUS
133	XFER PIPE
134	XFER MCHMK
135	XFER UPPER
136	MCH NXT
137	PREFETCH
138	FETCH CAN EQ
139	Z FETCH CAN FALSE
140	Z FETCH NEXT IN LINE
141	Z FETCH T4 CONTINUE
142	INCREMENT
143	INDIC LATCH
144	DECREMENT
145	PLOAD CYCLE
146	HITLEX L
147	IR DISABLE
148	Reserved
149	LAT FETCH
150	LAT SELECT
151	LAT MEM CYCLE
152	LATCH CYCLE
153	LATCH EXEC
154	LDI REG/MEM
155	LDF FETCH
156	LDI EXEC
157	XFER MEM UNIT
158	LATCH AUX
159	PASS PARAMETER
160	SAVE R0
161	LATCH R0
162	SAVE R1
163	LATCH R1
164	LATCH DEST
165	LATCH SRC
166	GPU CHINT
167	GPU SLTI INT
168	GPU ENABLE STE
169	GPU DIS STITE
170	RESET MCU
171	SET HSCH MCH
172	SET PCI
173	SET LBP2
174	ST MEM CYCLE
175	LPC
176	HITCH DEC
177	HITCH NEXT
178	HITCH IR
179	Z WAIT CYCLE
180	WAIT CYCLE
181	WAIT FOR
182	LATCH RFPA
183	LATCH ARITH

Numeric Codes¶

Number	Description
37105	LAT CYCLE1
37106	LAT CYCLE2
37107	LAT CYCLE3
37108	LAT CYCLE4
37109	LAT CYCLE5
37110	LATCH I1
37111	LATCH T
37112	LATCH D1
37113	LATCH D2
37514	XFER RESULT
37515	XFER RAM
37516	XFER SPMEM
37517	XFER REG
37518	EXEC1
37519	EXEC2

ND - 30.013.02

Page 132¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Opcode	Mnemonic	Description	Attribute
000000	ABD	Absolute Value Double	D FB FALS
000001	A1D	Add One Double	DBL FALS
000002	ADD T	Add (Short)	INT SHRT S
000003	ADD L	Add (Long)	INT LNG R
000004	AND T	And (Short)	INT SHRT S
000005	AND L	And (Long)	INT LNG R
000006	ASHM	Arithmetic Shift	INT LNG T
000007	ASHTL	Arithmetic Shift Left	LNG SHFT
000008	ASHTR	Arithmetic Shift Right	LNG SHFT

... (The pattern in the content suggests that these values continue sequentially with similar formatting, expanding the table accordingly to the actual document data available.)

Page 133¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

Value	Datatype
0.00000	0000000; 0000000; 2
0.00000	0000000; 0000000; 2
0.00000	0000000; 0000000; 2
0.00000	0000000; 0000000; 2

ND - 30.013.02

Page 134¶

ND-500 Micro Mnemonics¶

In Alphabetical and Numerical Order¶

Page	Document Number
117	ND - 30.013.02

Page 135¶

ND-500 Micro Mnemonics in Alphabetical and Numerical Order¶

ND - 30.013.02

Page 136¶

Index¶

ALT	3
ARITH	63
BOU	3
BREAK	6, 38, 41
characters	27
cache	16
CDB	3
CLKD	8
COMTE	35
CONTROL	5, 36, 40, 44
CSCNT	7, 38, 41
DATA	6, 37, 39, 43, 44
DATAIN	6, 37, 38, 45
DATAOUT	6, 37, 38, 45
DATAX	6
DBU	3
DCINHLL	19
DCINHLU	19
DCONO	18
DCON1	18
DOUB	3
DRADDRL	19
DRADDRM	19
DSTS0	17
DSTS1	17
DSTS2	17
DUEN	3
DUPL	19
DUT	3
DZPA	19
executing
sequence	29
EXTRA	85
GMENT	75
GMOFF	71
HAREM	26
HL	19
ICINHLL	19
ICINHLU	19
ICON0	18
ICON1	18
IOX	8
IRADDRL	19
IRADDRM	19
ISTS0	18
ISTS1	18
ISTS2	18
IUPL	19
IZPA	19
LCON	9
LL	7, 19, 37, 40, 45

Page 137¶

Index¶

Term	Page Numbers
LMAR	9
LSTA	9
MAR	5, 7, 37, 39, 43, 44
Master
clear	9
MCLR	9
MEMIC	53
memory	16
MM	3
MMOD	18
mode	28
MOST	3, 6, 8, 41, 42
MPEST	53
NOMAN	67
OPR	3
part
number	12
PREEF	59
PSTAT	13
RCON	9
Read
controlstore	12
data	10
RETG	9
RLOW	9
RMAR	9
RSTA	9
RTAG	9
SLICE	47
SLOC	9
STATUS	5, 37, 40, 43, 44
TAGIN	7
TAGOUT	8, 38, 41
TE	3
TERM	9
TRAPT	79
TSB	3
UL	7, 37, 40, 45
UNLC	9
useful
microinstructions	33
user
microprogram	31
register	28
WA	3, 6, 37, 41
WDAT	9
Write
controlstore	12
data	10
tag	10
WTAG	9

Page 138¶

I'm unable to provide details from the image, but based on the description, here's a possible layout:

Systems That Put People First¶

ND

Feel free to adjust the content as needed.

LOCATE	TYPE	RF	REG	Z	-1	0	1	VALUE	Z	LEAST	SIGN	MOST	SIGN.
A	J	N	Z	A	A	A	A	A	Z	A	A	A	A
A	J	Z	Z	+	A	A	A	A	J	J	J	J	J
A	AR	N	Z	J	A	A	A	+	J	+	Z	Z	Z
A	AR	A	Z	J	A	A	A	*	Z	*	*	*	*
A	AR	N	Z	*	Z	J	A	J	*	J	Z	Z	Z


ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD
SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB
MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL
DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV
AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND
OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR
XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR
NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT

LOCATE	TYPE	RF	REG	Z	-1	0	1	VALUE	Z	LEAST	SIGN	MOST	SIGN.
A	J	N	Z	A	A	A	A	A	Z	A	A	A	A
A	J	Z	Z	+	A	A	A	A	J	J	J	J	J
A	AR	N	Z	J	A	A	A	+	J	+	Z	Z	Z
A	AR	A	Z	J	A	A	A	*	Z	*	*	*	*
A	AR	N	Z	*	Z	J	A	J	*	J	Z	Z	Z


ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD
SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB
MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL
DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV
AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND
OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR
XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR
NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT

Page 1¶

Test Micro Program Descriptions for ND-500¶

Page 2¶

Test Micro Program¶

Descriptions for¶

ND-500¶

Page 3¶

Notice¶

Page 4¶

PRINTING RECORD¶

Page 5¶

Manual Updates¶

Page 6¶

PREFACE¶

THE PRODUCT¶

THE READER¶

PREREQUISITE KNOWLEDGE¶

THE MANUAL¶

Page 7¶

Related Manuals¶

Acknowledgement¶

Page 8¶

TABLE OF CONTENTS¶

Page 9¶

Section¶

4. How to use the programs.¶

Page 10¶

Section¶

6. COMTE - the ND-100/ND-500 communication test program.¶

6.4. The verification routines.¶

Page 11¶

Section¶

6.5. The micro programmed routines.¶

7. SLICE - the ND-500 slice test program.¶

Page 12¶

Section¶

8. MEMTC - the ND-500 cache and memory test program.¶

9. PREEF - the ND-500 prefetch processor test program.¶

Page 13¶

Section¶

9.3. The test routines.¶

9.4. The verification routines.¶

10. ARITH - The ND-500 external arithmetic test program.¶

10.1. General information.¶

10.2. How to load and start the program.¶

10.3. The test routines.¶

10.4. The verification routines.¶

Page 14¶

Section¶

11. NOMAN - the ND-500 no-memory-management test program.¶

11.1. General information.¶

11.2. How to load and start the program.¶

11.3. The test routines.¶

11.3.1. TST01 Test no-memory-management registers¶

11.4. The verification routines.¶

11.4.1. TST02 Verify DCINHL-DClNlHJ-DZPA-DUPL.¶

11.4.2. TST03 Verify ICINHLH-ICINHLJ-IZPA-IUPL.¶

11.4.3. TST04 Verify DRADDRM and DRADDRL.¶

11.4.4. TST05 Verify IRADDRM and IRADDRL.¶

11.4.5. TST06 Verify cache inhibit for data memory.¶

11.4.6. TST07 Verify cache inhibit for instruction memory.¶

11.4.7. TST08 Verify that read and write only affects the DZPA-DUPL area.¶

11.4.8. TST09 Verify that read and write only affects the IZPA-IUPL area.¶

11.4.9. TST10 Verify data cache clear.¶

11.4.10. TST11 Verify instruction cache clear.¶

12. GMOFF - the ND-500 memory-management-off test program.¶

12.1. General information.¶

12.2. How to load and start the program.¶

12.3. The test routines.¶

12.3.1. TST01 Not yet implemented.¶

12.3.2. TST02 Dump routine for IWTIPGU/DWIPGU.¶

12.4. The verification routines.¶

12.4.1. TST03 Verify data scratch file (DSCFA and DSCRF).¶

12.4.2. TST04 Verify instr. scratch file (ISCFA and ISCRF).¶

12.4.3. TST05 Verify DLADDR and DRADDR.¶

12.4.4. TST06 Verify ILADDR and IRADDR.¶

12.4.5. TST07 Verify WIP-buffer for data memory (DWIPGU).¶

12.4.6. TST08 Verify PGU-buffer for data memory (DWIPGU).¶

12.4.7. TST09 Verify WIP-buffer for instr. memory (IWIPGU).¶

Page 15¶

LOCATE	TYPE	RF	REG	Z	-1	0	1	VALUE	Z	LEAST	SIGN	MOST	SIGN.
A	J	N	Z	A	A	A	A	A	Z	A	A	A	A
A	J	Z	Z	+	A	A	A	A	J	J	J	J	J
A	AR	N	Z	J	A	A	A	+	J	+	Z	Z	Z
A	AR	A	Z	J	A	A	A	*	Z	*	*	*	*
A	AR	N	Z	*	Z	J	A	J	*	J	Z	Z	Z


ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD	ADD
SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB	SUB
MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL	MUL
DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV	DIV
AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND	AND
OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR	OR
XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR	XOR
NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT	NOT